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abc9_ops -prep_dff cope with lack of holes module

This commit is contained in:
Eddie Hung 2019-12-30 22:58:39 -08:00
parent a367f703ea
commit f1bf44ae8f
1 changed files with 38 additions and 38 deletions
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4
passes/techmap/abc9_ops.cc
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@ -137,8 +137,7 @@ void prep_dff(RTLIL::Module *module)
}
RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
log_assert(holes_module);
if (holes_module) {
dict<SigSig, SigSig> replace;
for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
auto cell = it->second;
@ -180,6 +179,7 @@ void prep_dff(RTLIL::Module *module)
conn = it->second;
}
}
}
void prep_holes(RTLIL::Module *module)
{