mirror of https://github.com/YosysHQ/yosys.git
add -noalu and -json option for apicula
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2116c58581
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@ -44,6 +44,11 @@ struct SynthGowinPass : public ScriptPass
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log(" write the design to the specified Verilog netlist file. writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON netlist file. writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log(" This disables features not yet supported by nexpnr-gowin.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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@ -70,6 +75,9 @@ struct SynthGowinPass : public ScriptPass
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log(" -noiopads\n");
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log(" do not emit IOB at top level ports\n");
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log("\n");
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log(" -noalu\n");
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log(" do not use ALU cells\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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@ -79,13 +87,14 @@ struct SynthGowinPass : public ScriptPass
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log("\n");
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}
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string top_opt, vout_file;
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bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
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string top_opt, vout_file, json_file;
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bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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vout_file = "";
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json_file = "";
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retime = false;
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flatten = true;
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nobram = false;
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@ -94,6 +103,7 @@ struct SynthGowinPass : public ScriptPass
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nowidelut = false;
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abc9 = false;
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noiopads = false;
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noalu = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -112,6 +122,14 @@ struct SynthGowinPass : public ScriptPass
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vout_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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nobram = true;
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nolutram = true;
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nowidelut = true;
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noalu = true;
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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@ -144,6 +162,10 @@ struct SynthGowinPass : public ScriptPass
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nowidelut = true;
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continue;
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}
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if (args[argidx] == "-noalu") {
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noalu = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc9 = true;
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continue;
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@ -210,7 +232,11 @@ struct SynthGowinPass : public ScriptPass
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if (check_label("map_gates"))
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{
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if (noalu) {
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run("techmap -map +/techmap.v");
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} else {
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run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
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}
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run("opt -fast");
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if (retime || help_mode)
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run("abc -dff -D 1", "(only if -retime)");
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@ -270,6 +296,9 @@ struct SynthGowinPass : public ScriptPass
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if (!vout_file.empty() || help_mode)
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run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s",
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help_mode ? "<file-name>" : vout_file.c_str()));
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s",
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help_mode ? "<file-name>" : json_file.c_str()));
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}
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}
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} SynthGowinPass;
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