mirror of https://github.com/YosysHQ/yosys.git
Improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -97,7 +97,8 @@ void rmunused_module_cells(Module *module, bool verbose)
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for (auto &it : module->cells_) {
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for (auto &it : module->cells_) {
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Cell *cell = it.second;
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Cell *cell = it.second;
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for (auto &it2 : cell->connections()) {
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for (auto &it2 : cell->connections()) {
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if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first))
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if (ct_all.cell_known(cell->type) && !ct_all.cell_output(cell->type, it2.first))
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continue;
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for (auto raw_bit : it2.second) {
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for (auto raw_bit : it2.second) {
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if (raw_bit.wire == nullptr)
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if (raw_bit.wire == nullptr)
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continue;
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continue;
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@ -109,9 +110,6 @@ void rmunused_module_cells(Module *module, bool verbose)
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if (bit.wire != nullptr)
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if (bit.wire != nullptr)
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wire2driver[bit].insert(cell);
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wire2driver[bit].insert(cell);
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}
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}
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if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it2.first))
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for (auto raw_bit : it2.second)
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used_raw_bits.insert(raw_bit);
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}
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}
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if (keep_cache.query(cell))
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if (keep_cache.query(cell))
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queue.insert(cell);
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queue.insert(cell);
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@ -130,12 +128,6 @@ void rmunused_module_cells(Module *module, bool verbose)
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}
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}
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}
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}
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for (auto it : driver_driver_logs) {
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if (used_raw_bits.count(it.first))
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for (auto msg : it.second)
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log_warning("%s\n", msg.c_str());
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}
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while (!queue.empty())
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while (!queue.empty())
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{
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{
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pool<SigBit> bits;
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pool<SigBit> bits;
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@ -161,6 +153,22 @@ void rmunused_module_cells(Module *module, bool verbose)
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module->remove(cell);
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module->remove(cell);
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count_rm_cells++;
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count_rm_cells++;
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}
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}
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for (auto &it : module->cells_) {
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Cell *cell = it.second;
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for (auto &it2 : cell->connections()) {
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if (ct_all.cell_known(cell->type) && !ct_all.cell_input(cell->type, it2.first))
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continue;
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for (auto raw_bit : it2.second)
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used_raw_bits.insert(raw_bit);
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}
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}
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for (auto it : driver_driver_logs) {
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if (used_raw_bits.count(it.first))
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for (auto msg : it.second)
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log_warning("%s\n", msg.c_str());
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}
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}
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}
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int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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