riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix out-of-tree builds configured as `SMALL := 1`.

This commit is contained in:
whitequark 2020-04-24 23:26:26 +00:00
parent 26cda3c247
commit f1087b2552
1 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
Makefile
View File

@ -584,10 +584,10 @@ include $(YOSYS_SRC)/techlibs/*/Makefile.inc
else else
include frontends/verilog/Makefile.inc include $(YOSYS_SRC)/frontends/verilog/Makefile.inc
include frontends/ilang/Makefile.inc include $(YOSYS_SRC)/frontends/ilang/Makefile.inc
include frontends/ast/Makefile.inc include $(YOSYS_SRC)/frontends/ast/Makefile.inc
include frontends/blif/Makefile.inc include $(YOSYS_SRC)/frontends/blif/Makefile.inc
OBJS += passes/hierarchy/hierarchy.o OBJS += passes/hierarchy/hierarchy.o
OBJS += passes/cmds/select.o OBJS += passes/cmds/select.o
@ -597,14 +597,14 @@ OBJS += passes/cmds/cover.o
OBJS += passes/cmds/design.o OBJS += passes/cmds/design.o
OBJS += passes/cmds/plugin.o OBJS += passes/cmds/plugin.o
include passes/proc/Makefile.inc include $(YOSYS_SRC)/passes/proc/Makefile.inc
include passes/opt/Makefile.inc include $(YOSYS_SRC)/passes/opt/Makefile.inc
include passes/techmap/Makefile.inc include $(YOSYS_SRC)/passes/techmap/Makefile.inc
include backends/verilog/Makefile.inc include $(YOSYS_SRC)/backends/verilog/Makefile.inc
include backends/ilang/Makefile.inc include $(YOSYS_SRC)/backends/ilang/Makefile.inc
include techlibs/common/Makefile.inc include $(YOSYS_SRC)/techlibs/common/Makefile.inc
endif endif