riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

opt_share: Fix input confusion with ANDNOT, ORNOT gates 

Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_`
gates when considering those for sharing. Unlike the input ports of the
other supported single-bit gates, those are not interchangeable.

Fixes #3848.
This commit is contained in:
Martin Povišer 2023-07-19 20:08:22 +02:00 committed by Lofty
parent 83c9261d6c
commit f0ae046c5a
2 changed files with 31 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
passes/opt/opt_share.cc
View File

@ -131,6 +131,9 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B)
return port_name;
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
return port_name;
return "";
}

28
tests/opt/bug3848.ys Normal file
View File

@ -0,0 +1,28 @@
read_verilog -icells <<EOF
module test(a, b, s, y);
input a, b, s;
output y;
wire f, g;
$_ANDNOT_ g1(.A(a), .B(b), .Y(f));
$_ANDNOT_ g2(.A(b), .B(a), .Y(g));
$_MUX_ m(.A(f), .B(g), .S(s), .Y(y));
endmodule
EOF
equiv_opt -assert opt_share
design -reset
read_verilog -icells <<EOF
module test(a, b, s, y);
input a, b, s;
output y;
wire f, g;
$_ORNOT_ g1(.A(a), .B(b), .Y(f));
$_ORNOT_ g2(.A(b), .B(a), .Y(g));
$_MUX_ m(.A(f), .B(g), .S(s), .Y(y));
endmodule
EOF
equiv_opt -assert opt_share