From f050c405190c50d2c1aed22644a9a207445e6592 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 7 Nov 2013 09:58:15 +0100 Subject: [PATCH] Various fixes for correct parameter support --- frontends/ast/ast.cc | 4 +- frontends/ast/genrtlil.cc | 34 ++++++++++------ frontends/ast/simplify.cc | 25 ++++++++++++ frontends/verilog/parser.y | 80 +++++++++++++++++++++++++------------- 4 files changed, 102 insertions(+), 41 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 51dcd34ac..bf7d0c38c 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -814,8 +814,8 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::mapstr.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str]))); rewrite_parameter: para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); - child->delete_children(); - child->children.push_back(AstNode::mkconst_bits(parameters[para_id].bits, false)); + delete child->children.at(0); + child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, child->is_signed); hash_data.insert(hash_data.end(), child->str.begin(), child->str.end()); hash_data.push_back(0); hash_data.insert(hash_data.end(), parameters[para_id].bits.begin(), parameters[para_id].bits.end()); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 0fde9b3b9..f69ca69ea 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -562,6 +562,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint) int sub_width_hint = -1; int this_width = 0; AstNode *range = NULL; + AstNode *id_ast = NULL; switch (type) { @@ -572,15 +573,24 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint) break; case AST_IDENTIFIER: - if (!id2ast) + id_ast = id2ast; + if (id_ast == NULL && current_scope.count(str)) + id_ast = current_scope.at(str); + if (!id_ast) log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", str.c_str(), filename.c_str(), linenum); - if ((id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) && id2ast->children[0]->type == AST_CONSTANT) { - this_width = id2ast->children[0]->bits.size(); + if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) { + if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { + this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; + } else + if (id_ast->children[0]->type == AST_CONSTANT) { + this_width = id_ast->children[0]->bits.size(); + } else + log_error("Failed to detect width for parameter %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum); if (children.size() != 0) range = children[0]; - } else if (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE) { - if (!id2ast->range_valid) { - if (id2ast->type == AST_AUTOWIRE) + } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) { + if (!id_ast->range_valid) { + if (id_ast->type == AST_AUTOWIRE) this_width = 1; else { current_ast_mod->dumpAst(stdout, ""); @@ -590,16 +600,16 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint) log_error("Failed to detect with of signal access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); } } else { - this_width = id2ast->range_left - id2ast->range_right + 1; + this_width = id_ast->range_left - id_ast->range_right + 1; if (children.size() != 0) range = children[0]; } - } else if (id2ast->type == AST_GENVAR) { + } else if (id_ast->type == AST_GENVAR) { this_width = 32; - } else if (id2ast->type == AST_MEMORY) { - if (!id2ast->children[0]->range_valid) + } else if (id_ast->type == AST_MEMORY) { + if (!id_ast->children[0]->range_valid) log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); - this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1; + this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1; } else log_error("Failed to detect width for identifier %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum); if (range) { @@ -620,7 +630,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint) this_width = range->range_left - range->range_right + 1; } else width_hint = std::max(width_hint, this_width); - if (!id2ast->is_signed) + if (!id_ast->is_signed) sign_hint = false; break; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 81812a40f..d34960481 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -197,6 +197,18 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, child_0_is_self_determined = true; break; + case AST_PARAMETER: + case AST_LOCALPARAM: + children[0]->detectSignWidth(width_hint, sign_hint); + if (children.size() > 1) { + assert(children[1]->type == AST_RANGE); + while (children[1]->simplify(false, false, false, stage, -1, false) == true) { } + if (!children[1]->range_valid) + log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum); + width_hint = std::max(width_hint, children[1]->range_left - children[1]->range_right + 1); + } + break; + case AST_TO_SIGNED: case AST_TO_UNSIGNED: case AST_CONCAT: @@ -419,6 +431,19 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } } + // trim/extend parameters + if ((type == AST_PARAMETER || type == AST_LOCALPARAM) && children[0]->type == AST_CONSTANT && children.size() > 1) { + if (!children[1]->range_valid) + log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum); + int width = children[1]->range_left - children[1]->range_right + 1; + if (width != int(children[0]->bits.size())) { + RTLIL::SigSpec sig(children[0]->bits); + sig.extend(width, children[0]->is_signed); + delete children[0]; + children[0] = mkconst_bits(sig.as_const().bits, children[0]->is_signed); + } + } + // annotate identifiers using scope resolution and create auto-wires as needed if (type == AST_IDENTIFIER) { if (current_scope.count(str) == 0) { diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 35e225179..666948987 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -225,10 +225,18 @@ module_para_opt: '#' '(' module_para_list ')' | /* empty */; module_para_list: - TOK_PARAMETER single_param_decl | - TOK_PARAMETER single_param_decl ',' module_para_list | + single_module_para | + single_module_para ',' module_para_list | /* empty */; +single_module_para: + TOK_PARAMETER { + astbuf1 = new AstNode(AST_PARAMETER); + astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + } param_signed param_integer param_range single_param_decl { + delete astbuf1; + }; + module_args_opt: '(' ')' | /* empty */ | '(' module_args optional_comma ')'; @@ -368,38 +376,56 @@ task_func_body: task_func_body behavioral_stmt | /* empty */; +param_signed: + TOK_SIGNED { + astbuf1->is_signed = true; + } | /* empty */; + +param_integer: + TOK_INTEGER { + if (astbuf1->children.size() != 1) + frontend_verilog_yyerror("Syntax error."); + astbuf1->children.push_back(new AstNode(AST_RANGE)); + astbuf1->children[0]->children.push_back(AstNode::mkconst_int(31, true)); + astbuf1->children[0]->children.push_back(AstNode::mkconst_int(0, true)); + } | /* empty */; + +param_range: + range { + if ($1 != NULL) { + if (astbuf1->children.size() != 1) + frontend_verilog_yyerror("Syntax error."); + astbuf1->children.push_back($1); + } + }; + param_decl: - TOK_PARAMETER param_decl_list ';'; + TOK_PARAMETER { + astbuf1 = new AstNode(AST_PARAMETER); + astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + } param_signed param_integer param_range param_decl_list ';' { + delete astbuf1; + }; + +localparam_decl: + TOK_LOCALPARAM { + astbuf1 = new AstNode(AST_LOCALPARAM); + astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + } param_signed param_integer param_range param_decl_list ';' { + delete astbuf1; + }; param_decl_list: single_param_decl | param_decl_list ',' single_param_decl; single_param_decl: - range TOK_ID '=' expr { - AstNode *node = new AstNode(AST_PARAMETER); - node->str = *$2; - node->children.push_back($4); - if ($1 != NULL) - node->children.push_back($1); + TOK_ID '=' expr { + AstNode *node = astbuf1->clone(); + node->str = *$1; + delete node->children[0]; + node->children[0] = $3; ast_stack.back()->children.push_back(node); - delete $2; - }; - -localparam_decl: - TOK_LOCALPARAM localparam_decl_list ';'; - -localparam_decl_list: - single_localparam_decl | localparam_decl_list ',' single_localparam_decl; - -single_localparam_decl: - range TOK_ID '=' expr { - AstNode *node = new AstNode(AST_LOCALPARAM); - node->str = *$2; - node->children.push_back($4); - if ($1 != NULL) - node->children.push_back($1); - ast_stack.back()->children.push_back(node); - delete $2; + delete $1; }; defparam_decl: