From 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9 Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Thu, 14 May 2020 14:38:13 +0200 Subject: [PATCH] Add support for non-power-of-two mem chunks in verific importer Signed-off-by: Claire Wolf --- frontends/verific/verific.cc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fe4bda68e..5f8a78e48 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1265,7 +1265,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->OutputSize()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0) + if ((numchunks * memory->width) != int(inst->OutputSize())) log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); for (int i = 0; i < numchunks; i++) @@ -1273,6 +1273,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); + if ((numchunks & (numchunks - 1)) != 0) { + addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks)); + addr = module->Add(NEW_ID, addr, RTLIL::Const(i)); + } + RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd)); cell->parameters[ID::MEMID] = memory->name.str(); @@ -1295,7 +1300,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->Input2Size()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0) + if ((numchunks * memory->width) != int(inst->Input2Size())) log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); for (int i = 0; i < numchunks; i++) @@ -1303,6 +1308,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width); + if ((numchunks & (numchunks - 1)) != 0) { + addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks)); + addr = module->Add(NEW_ID, addr, RTLIL::Const(i)); + } + RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr)); cell->parameters[ID::MEMID] = memory->name.str();