riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

unmap $__ICE40_CARRY_WRAPPER in test

This commit is contained in:
Eddie Hung 2019-12-09 14:20:35 -08:00
parent bbdf2452b3
commit eff858cd33
1 changed files with 21 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
tests/arch/ice40/ice40_opt.ys
View File

@ -1,3 +1,23 @@
read_verilog -icells -formal <<EOT
module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
\$lut #(
.WIDTH(4),
.LUT(LUT)
) lut (
.A({I0,A,B,I3}),
.Y(O)
);
endmodule
EOT
design -stash unmap
read_verilog -icells -formal <<EOT read_verilog -icells -formal <<EOT
module top(input CI, I0, output [1:0] CO, output O); module top(input CI, I0, output [1:0] CO, output O);
wire A = 1'b0, B = 1'b0; wire A = 1'b0, B = 1'b0;
@ -20,7 +40,7 @@ module top(input CI, I0, output [1:0] CO, output O);
endmodule endmodule
EOT EOT
equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
design -load postopt design -load postopt
select -assert-count 1 t:* select -assert-count 1 t:*
select -assert-count 1 t:$lut select -assert-count 1 t:$lut