riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

write_xaiger to skip POs driven by 1'bx

This commit is contained in:
Eddie Hung 2019-06-20 10:21:57 -07:00
parent cdbcd2efbd
commit efdb057c6a
1 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
backends/aiger/xaiger.cc
View File

@ -152,9 +152,13 @@ struct XAigerWriter
} }
if (wire->port_output || keep) { if (wire->port_output || keep) {
if (bit != wirebit) if (bit != RTLIL::Sx) {
alias_map[wirebit] = bit; if (bit != wirebit)
output_bits.insert(wirebit); alias_map[wirebit] = bit;
output_bits.insert(wirebit);
}
else
log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
} }
} }
} }