mirror of https://github.com/YosysHQ/yosys.git
Implemented "scc -set_attr"
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914aa8a5d3
commit
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@ -246,11 +246,9 @@ struct SccPass : public Pass {
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log(" are assumed to be bidirectional 'inout' ports.\n");
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log(" are assumed to be bidirectional 'inout' ports.\n");
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log("\n");
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log("\n");
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log(" -set_attr <name> <value>\n");
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log(" -set_attr <name> <value>\n");
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log(" -set_cell_attr <name> <value>\n");
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log(" set the specified attribute on all cells that are part of a logic\n");
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log(" -set_wire_attr <name> <value>\n");
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log(" loop. the special token {} in the value is replaced with a unique\n");
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log(" set the specified attribute on all cells and/or wires that are part of\n");
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log(" identifier for the logic loop.\n");
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log(" a logic loop. the special token {} in the value is replaced with a\n");
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log(" unique identifier for the logic loop.\n");
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log("\n");
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log("\n");
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log(" -select\n");
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log(" -select\n");
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log(" replace the current selection with a selection of all cells and wires\n");
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log(" replace the current selection with a selection of all cells and wires\n");
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@ -259,7 +257,7 @@ struct SccPass : public Pass {
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}
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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{
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std::map<std::string, std::string> setCellAttr, setWireAttr;
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std::map<std::string, std::string> setAttr;
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bool allCellTypes = false;
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bool allCellTypes = false;
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bool selectMode = false;
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bool selectMode = false;
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bool nofeedbackMode = false;
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bool nofeedbackMode = false;
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@ -287,18 +285,7 @@ struct SccPass : public Pass {
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continue;
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continue;
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}
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}
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if (args[argidx] == "-set_attr" && argidx+2 < args.size()) {
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if (args[argidx] == "-set_attr" && argidx+2 < args.size()) {
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setCellAttr[args[argidx+1]] = args[argidx+2];
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setAttr[args[argidx+1]] = args[argidx+2];
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setWireAttr[args[argidx+1]] = args[argidx+2];
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argidx += 2;
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continue;
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}
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if (args[argidx] == "-set_cell_attr" && argidx+2 < args.size()) {
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setCellAttr[args[argidx+1]] = args[argidx+2];
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argidx += 2;
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continue;
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}
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if (args[argidx] == "-set_wire_attr" && argidx+2 < args.size()) {
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setWireAttr[args[argidx+1]] = args[argidx+2];
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argidx += 2;
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argidx += 2;
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continue;
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continue;
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}
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}
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@ -311,9 +298,6 @@ struct SccPass : public Pass {
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int origSelectPos = design->selection_stack.size() - 1;
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int origSelectPos = design->selection_stack.size() - 1;
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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if (setCellAttr.size() > 0 || setWireAttr.size() > 0)
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log_cmd_error("The -set*_attr options are not implemented at the moment!\n");
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RTLIL::Selection newSelection(false);
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RTLIL::Selection newSelection(false);
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int scc_counter = 0;
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int scc_counter = 0;
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@ -321,7 +305,33 @@ struct SccPass : public Pass {
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if (design->selected(mod_it.second))
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if (design->selected(mod_it.second))
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{
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{
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SccWorker worker(design, mod_it.second, nofeedbackMode, allCellTypes, maxDepth);
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SccWorker worker(design, mod_it.second, nofeedbackMode, allCellTypes, maxDepth);
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scc_counter += GetSize(worker.sccList);
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if (!setAttr.empty())
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{
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for (const auto &cells : worker.sccList)
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{
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for (auto attr : setAttr)
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{
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IdString attr_name(RTLIL::escape_id(attr.first));
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string attr_valstr = attr.second;
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string index = stringf("%d", scc_counter);
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for (size_t pos = 0; (pos = attr_valstr.find("{}", pos)) != string::npos; pos += index.size())
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attr_valstr.replace(pos, 2, index);
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Const attr_value(attr_valstr);
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for (auto cell : cells)
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cell->attributes[attr_name] = attr_value;
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}
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scc_counter++;
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}
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}
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else
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{
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scc_counter += GetSize(worker.sccList);
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}
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if (selectMode)
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if (selectMode)
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worker.select(newSelection);
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worker.select(newSelection);
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