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Merge branch 'master' of github.com:YosysHQ/yosys

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Clifford Wolf 2018-11-12 09:10:25 +01:00
parent d1372873e8 dbc4cb8f4a
commit ef1c61aae4
4 changed files with 1044 additions and 1 deletions
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419
techlibs/ecp5/cells_bb.v
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@ -93,3 +93,422 @@ module ALU54B(
parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
parameter LEGACY = "DISABLED"; parameter LEGACY = "DISABLED";
endmodule endmodule
(* blackbox *)
module EHXPLLL (
input CLKI, CLKFB,
input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,
input STDBY, PLLWAKESYNC,
input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,
output CLKOP, CLKOS, CLKOS2, CLKOS3,
output LOCK, INTLOCK,
output REFCLK, CLKINTFB
);
parameter CLKI_DIV = 1;
parameter CLKFB_DIV = 1;
parameter CLKOP_DIV = 8;
parameter CLKOS_DIV = 8;
parameter CLKOS2_DIV = 8;
parameter CLKOS3_DIV = 8;
parameter CLKOP_ENABLE = "ENABLED";
parameter CLKOS_ENABLE = "DISABLED";
parameter CLKOS2_ENABLE = "DISABLED";
parameter CLKOS3_ENABLE = "DISABLED";
parameter CLKOP_CPHASE = 0;
parameter CLKOS_CPHASE = 0;
parameter CLKOS2_CPHASE = 0;
parameter CLKOS3_CPHASE = 0;
parameter CLKOP_FPHASE = 0;
parameter CLKOS_FPHASE = 0;
parameter CLKOS2_FPHASE = 0;
parameter CLKOS3_FPHASE = 0;
parameter FEEDBK_PATH = "CLKOP";
parameter CLKOP_TRIM_POL = "RISING";
parameter CLKOP_TRIM_DELAY = 0;
parameter CLKOS_TRIM_POL = "RISING";
parameter CLKOS_TRIM_DELAY = 0;
parameter OUTDIVIDER_MUXA = "DIVA";
parameter OUTDIVIDER_MUXB = "DIVB";
parameter OUTDIVIDER_MUXC = "DIVC";
parameter OUTDIVIDER_MUXD = "DIVD";
parameter PLL_LOCK_MODE = 0;
parameter PLL_LOCK_DELAY = 200;
parameter STDBY_ENABLE = "DISABLED";
parameter REFIN_RESET = "DISABLED";
parameter SYNC_ENABLE = "DISABLED";
parameter INT_LOCK_STICKY = "ENABLED";
parameter DPHASE_SOURCE = "DISABLED";
parameter PLLRST_ENA = "DISABLED";
parameter INTFB_WAKE = "DISABLED";
endmodule
(* blackbox *)
module DTR(
input STARTPULSE,
output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0
);
endmodule
(* blackbox *)
module OSCG(
output OSC
);
parameter DIV = 128;
endmodule
(* blackbox *)
module IDDRX1F(
input D, SCLK, RST,
output Q0, Q1
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX1F(
input SCLK, RST, D0, D1,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module CLKDIVF(
input CLKI, RST, ALIGNWD,
output CDIVX
);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
endmodule
(* blackbox *)
module DCCA(
input CLKI, CE,
output CLKO
);
endmodule
(* blackbox *) (* keep *)
module DCUA(
input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN,
input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,
input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,
input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,
input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,
input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,
input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,
input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,
input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,
input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,
input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,
input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,
input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,
input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,
input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,
input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,
input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,
input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,
input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,
input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,
output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,
output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,
output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,
output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,
output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,
output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,
output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,
output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,
output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,
output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,
output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,
output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,
output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,
output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,
input D_REFCLKI,
output D_FFS_PLOL
);
parameter CH0_AUTO_CALIB_EN = "0b0";
parameter CH0_AUTO_FACQ_EN = "0b0";
parameter CH0_BAND_THRESHOLD = "0b000000";
parameter CH0_CALIB_CK_MODE = "0b0";
parameter CH0_CC_MATCH_1 = "0b0000000000";
parameter CH0_CC_MATCH_2 = "0b0000000000";
parameter CH0_CC_MATCH_3 = "0b0000000000";
parameter CH0_CC_MATCH_4 = "0b0000000000";
parameter CH0_CDR_CNT4SEL = "0b00";
parameter CH0_CDR_CNT8SEL = "0b00";
parameter CH0_CTC_BYPASS = "0b0";
parameter CH0_DCOATDCFG = "0b00";
parameter CH0_DCOATDDLY = "0b00";
parameter CH0_DCOBYPSATD = "0b0";
parameter CH0_DCOCALDIV = "0b000";
parameter CH0_DCOCTLGI = "0b000";
parameter CH0_DCODISBDAVOID = "0b0";
parameter CH0_DCOFLTDAC = "0b00";
parameter CH0_DCOFTNRG = "0b000";
parameter CH0_DCOIOSTUNE = "0b000";
parameter CH0_DCOITUNE = "0b00";
parameter CH0_DCOITUNE4LSB = "0b000";
parameter CH0_DCOIUPDNX2 = "0b0";
parameter CH0_DCONUOFLSB = "0b000";
parameter CH0_DCOSCALEI = "0b00";
parameter CH0_DCOSTARTVAL = "0b000";
parameter CH0_DCOSTEP = "0b00";
parameter CH0_DEC_BYPASS = "0b0";
parameter CH0_ENABLE_CG_ALIGN = "0b0";
parameter CH0_ENC_BYPASS = "0b0";
parameter CH0_FF_RX_F_CLK_DIS = "0b0";
parameter CH0_FF_RX_H_CLK_EN = "0b0";
parameter CH0_FF_TX_F_CLK_DIS = "0b0";
parameter CH0_FF_TX_H_CLK_EN = "0b0";
parameter CH0_GE_AN_ENABLE = "0b0";
parameter CH0_INVERT_RX = "0b0";
parameter CH0_INVERT_TX = "0b0";
parameter CH0_LDR_CORE2TX_SEL = "0b0";
parameter CH0_LDR_RX2CORE_SEL = "0b0";
parameter CH0_LEQ_OFFSET_SEL = "0b0";
parameter CH0_LEQ_OFFSET_TRIM = "0b000";
parameter CH0_LSM_DISABLE = "0b0";
parameter CH0_MATCH_2_ENABLE = "0b0";
parameter CH0_MATCH_4_ENABLE = "0b0";
parameter CH0_MIN_IPG_CNT = "0b00";
parameter CH0_PCIE_EI_EN = "0b0";
parameter CH0_PCIE_MODE = "0b0";
parameter CH0_PCS_DET_TIME_SEL = "0b00";
parameter CH0_PDEN_SEL = "0b0";
parameter CH0_PRBS_ENABLE = "0b0";
parameter CH0_PRBS_LOCK = "0b0";
parameter CH0_PRBS_SELECTION = "0b0";
parameter CH0_RATE_MODE_RX = "0b0";
parameter CH0_RATE_MODE_TX = "0b0";
parameter CH0_RCV_DCC_EN = "0b0";
parameter CH0_REG_BAND_OFFSET = "0b0000";
parameter CH0_REG_BAND_SEL = "0b000000";
parameter CH0_REG_IDAC_EN = "0b0";
parameter CH0_REG_IDAC_SEL = "0b0000000000";
parameter CH0_REQ_EN = "0b0";
parameter CH0_REQ_LVL_SET = "0b00";
parameter CH0_RIO_MODE = "0b0";
parameter CH0_RLOS_SEL = "0b0";
parameter CH0_RPWDNB = "0b0";
parameter CH0_RTERM_RX = "0b00000";
parameter CH0_RTERM_TX = "0b00000";
parameter CH0_RXIN_CM = "0b00";
parameter CH0_RXTERM_CM = "0b00";
parameter CH0_RX_DCO_CK_DIV = "0b000";
parameter CH0_RX_DIV11_SEL = "0b0";
parameter CH0_RX_GEAR_BYPASS = "0b0";
parameter CH0_RX_GEAR_MODE = "0b0";
parameter CH0_RX_LOS_CEQ = "0b00";
parameter CH0_RX_LOS_EN = "0b0";
parameter CH0_RX_LOS_HYST_EN = "0b0";
parameter CH0_RX_LOS_LVL = "0b000";
parameter CH0_RX_RATE_SEL = "0b0000";
parameter CH0_RX_SB_BYPASS = "0b0";
parameter CH0_SB_BYPASS = "0b0";
parameter CH0_SEL_SD_RX_CLK = "0b0";
parameter CH0_TDRV_DAT_SEL = "0b00";
parameter CH0_TDRV_POST_EN = "0b0";
parameter CH0_TDRV_PRE_EN = "0b0";
parameter CH0_TDRV_SLICE0_CUR = "0b000";
parameter CH0_TDRV_SLICE0_SEL = "0b00";
parameter CH0_TDRV_SLICE1_CUR = "0b000";
parameter CH0_TDRV_SLICE1_SEL = "0b00";
parameter CH0_TDRV_SLICE2_CUR = "0b00";
parameter CH0_TDRV_SLICE2_SEL = "0b00";
parameter CH0_TDRV_SLICE3_CUR = "0b00";
parameter CH0_TDRV_SLICE3_SEL = "0b00";
parameter CH0_TDRV_SLICE4_CUR = "0b00";
parameter CH0_TDRV_SLICE4_SEL = "0b00";
parameter CH0_TDRV_SLICE5_CUR = "0b00";
parameter CH0_TDRV_SLICE5_SEL = "0b00";
parameter CH0_TPWDNB = "0b0";
parameter CH0_TX_CM_SEL = "0b00";
parameter CH0_TX_DIV11_SEL = "0b0";
parameter CH0_TX_GEAR_BYPASS = "0b0";
parameter CH0_TX_GEAR_MODE = "0b0";
parameter CH0_TX_POST_SIGN = "0b0";
parameter CH0_TX_PRE_SIGN = "0b0";
parameter CH0_UC_MODE = "0b0";
parameter CH0_UDF_COMMA_A = "0b0000000000";
parameter CH0_UDF_COMMA_B = "0b0000000000";
parameter CH0_UDF_COMMA_MASK = "0b0000000000";
parameter CH0_WA_BYPASS = "0b0";
parameter CH0_WA_MODE = "0b0";
parameter CH1_AUTO_CALIB_EN = "0b0";
parameter CH1_AUTO_FACQ_EN = "0b0";
parameter CH1_BAND_THRESHOLD = "0b000000";
parameter CH1_CALIB_CK_MODE = "0b0";
parameter CH1_CC_MATCH_1 = "0b0000000000";
parameter CH1_CC_MATCH_2 = "0b0000000000";
parameter CH1_CC_MATCH_3 = "0b0000000000";
parameter CH1_CC_MATCH_4 = "0b0000000000";
parameter CH1_CDR_CNT4SEL = "0b00";
parameter CH1_CDR_CNT8SEL = "0b00";
parameter CH1_CTC_BYPASS = "0b0";
parameter CH1_DCOATDCFG = "0b00";
parameter CH1_DCOATDDLY = "0b00";
parameter CH1_DCOBYPSATD = "0b0";
parameter CH1_DCOCALDIV = "0b000";
parameter CH1_DCOCTLGI = "0b000";
parameter CH1_DCODISBDAVOID = "0b0";
parameter CH1_DCOFLTDAC = "0b00";
parameter CH1_DCOFTNRG = "0b000";
parameter CH1_DCOIOSTUNE = "0b000";
parameter CH1_DCOITUNE = "0b00";
parameter CH1_DCOITUNE4LSB = "0b000";
parameter CH1_DCOIUPDNX2 = "0b0";
parameter CH1_DCONUOFLSB = "0b000";
parameter CH1_DCOSCALEI = "0b00";
parameter CH1_DCOSTARTVAL = "0b000";
parameter CH1_DCOSTEP = "0b00";
parameter CH1_DEC_BYPASS = "0b0";
parameter CH1_ENABLE_CG_ALIGN = "0b0";
parameter CH1_ENC_BYPASS = "0b0";
parameter CH1_FF_RX_F_CLK_DIS = "0b0";
parameter CH1_FF_RX_H_CLK_EN = "0b0";
parameter CH1_FF_TX_F_CLK_DIS = "0b0";
parameter CH1_FF_TX_H_CLK_EN = "0b0";
parameter CH1_GE_AN_ENABLE = "0b0";
parameter CH1_INVERT_RX = "0b0";
parameter CH1_INVERT_TX = "0b0";
parameter CH1_LDR_CORE2TX_SEL = "0b0";
parameter CH1_LDR_RX2CORE_SEL = "0b0";
parameter CH1_LEQ_OFFSET_SEL = "0b0";
parameter CH1_LEQ_OFFSET_TRIM = "0b000";
parameter CH1_LSM_DISABLE = "0b0";
parameter CH1_MATCH_2_ENABLE = "0b0";
parameter CH1_MATCH_4_ENABLE = "0b0";
parameter CH1_MIN_IPG_CNT = "0b00";
parameter CH1_PCIE_EI_EN = "0b0";
parameter CH1_PCIE_MODE = "0b0";
parameter CH1_PCS_DET_TIME_SEL = "0b00";
parameter CH1_PDEN_SEL = "0b0";
parameter CH1_PRBS_ENABLE = "0b0";
parameter CH1_PRBS_LOCK = "0b0";
parameter CH1_PRBS_SELECTION = "0b0";
parameter CH1_RATE_MODE_RX = "0b0";
parameter CH1_RATE_MODE_TX = "0b0";
parameter CH1_RCV_DCC_EN = "0b0";
parameter CH1_REG_BAND_OFFSET = "0b0000";
parameter CH1_REG_BAND_SEL = "0b000000";
parameter CH1_REG_IDAC_EN = "0b0";
parameter CH1_REG_IDAC_SEL = "0b0000000000";
parameter CH1_REQ_EN = "0b0";
parameter CH1_REQ_LVL_SET = "0b00";
parameter CH1_RIO_MODE = "0b0";
parameter CH1_RLOS_SEL = "0b0";
parameter CH1_RPWDNB = "0b0";
parameter CH1_RTERM_RX = "0b00000";
parameter CH1_RTERM_TX = "0b00000";
parameter CH1_RXIN_CM = "0b00";
parameter CH1_RXTERM_CM = "0b00";
parameter CH1_RX_DCO_CK_DIV = "0b000";
parameter CH1_RX_DIV11_SEL = "0b0";
parameter CH1_RX_GEAR_BYPASS = "0b0";
parameter CH1_RX_GEAR_MODE = "0b0";
parameter CH1_RX_LOS_CEQ = "0b00";
parameter CH1_RX_LOS_EN = "0b0";
parameter CH1_RX_LOS_HYST_EN = "0b0";
parameter CH1_RX_LOS_LVL = "0b000";
parameter CH1_RX_RATE_SEL = "0b0000";
parameter CH1_RX_SB_BYPASS = "0b0";
parameter CH1_SB_BYPASS = "0b0";
parameter CH1_SEL_SD_RX_CLK = "0b0";
parameter CH1_TDRV_DAT_SEL = "0b00";
parameter CH1_TDRV_POST_EN = "0b0";
parameter CH1_TDRV_PRE_EN = "0b0";
parameter CH1_TDRV_SLICE0_CUR = "0b000";
parameter CH1_TDRV_SLICE0_SEL = "0b00";
parameter CH1_TDRV_SLICE1_CUR = "0b000";
parameter CH1_TDRV_SLICE1_SEL = "0b00";
parameter CH1_TDRV_SLICE2_CUR = "0b00";
parameter CH1_TDRV_SLICE2_SEL = "0b00";
parameter CH1_TDRV_SLICE3_CUR = "0b00";
parameter CH1_TDRV_SLICE3_SEL = "0b00";
parameter CH1_TDRV_SLICE4_CUR = "0b00";
parameter CH1_TDRV_SLICE4_SEL = "0b00";
parameter CH1_TDRV_SLICE5_CUR = "0b00";
parameter CH1_TDRV_SLICE5_SEL = "0b00";
parameter CH1_TPWDNB = "0b0";
parameter CH1_TX_CM_SEL = "0b00";
parameter CH1_TX_DIV11_SEL = "0b0";
parameter CH1_TX_GEAR_BYPASS = "0b0";
parameter CH1_TX_GEAR_MODE = "0b0";
parameter CH1_TX_POST_SIGN = "0b0";
parameter CH1_TX_PRE_SIGN = "0b0";
parameter CH1_UC_MODE = "0b0";
parameter CH1_UDF_COMMA_A = "0b0000000000";
parameter CH1_UDF_COMMA_B = "0b0000000000";
parameter CH1_UDF_COMMA_MASK = "0b0000000000";
parameter CH1_WA_BYPASS = "0b0";
parameter CH1_WA_MODE = "0b0";
parameter D_BITCLK_FROM_ND_EN = "0b0";
parameter D_BITCLK_LOCAL_EN = "0b0";
parameter D_BITCLK_ND_EN = "0b0";
parameter D_BUS8BIT_SEL = "0b0";
parameter D_CDR_LOL_SET = "0b00";
parameter D_CMUSETBIASI = "0b00";
parameter D_CMUSETI4CPP = "0b0000";
parameter D_CMUSETI4CPZ = "0b0000";
parameter D_CMUSETI4VCO = "0b00";
parameter D_CMUSETICP4P = "0b00";
parameter D_CMUSETICP4Z = "0b000";
parameter D_CMUSETINITVCT = "0b00";
parameter D_CMUSETISCL4VCO = "0b000";
parameter D_CMUSETP1GM = "0b000";
parameter D_CMUSETP2AGM = "0b000";
parameter D_CMUSETZGM = "0b000";
parameter D_DCO_CALIB_TIME_SEL = "0b00";
parameter D_HIGH_MARK = "0b0000";
parameter D_IB_PWDNB = "0b0";
parameter D_ISETLOS = "0b00000000";
parameter D_LOW_MARK = "0b0000";
parameter D_MACROPDB = "0b0";
parameter D_PD_ISET = "0b00";
parameter D_PLL_LOL_SET = "0b00";
parameter D_REFCK_MODE = "0b000";
parameter D_REQ_ISET = "0b000";
parameter D_RG_EN = "0b0";
parameter D_RG_SET = "0b00";
parameter D_SETICONST_AUX = "0b00";
parameter D_SETICONST_CH = "0b00";
parameter D_SETIRPOLY_AUX = "0b00";
parameter D_SETIRPOLY_CH = "0b00";
parameter D_SETPLLRC = "0b000000";
parameter D_SYNC_LOCAL_EN = "0b0";
parameter D_SYNC_ND_EN = "0b0";
parameter D_TXPLL_PWDNB = "0b0";
parameter D_TX_VCO_CK_DIV = "0b000";
parameter D_XGE_MODE = "0b0";
// These parameters don't do anything but are
// needed for compatability with Diamond
parameter D_TX_MAX_RATE = "2.5";
parameter D_RX_MAX_RATE = "2.5";
parameter CH0_TXAMPLITUDE = "0d1300";
parameter CH1_TXAMPLITUDE = "0d1300";
parameter CH0_PROTOCOL = "8B10B";
parameter CH1_PROTOCOL = "8B10B";
parameter CH0_CDR_MAX_RATE = "2.5";
parameter CH1_CDR_MAX_RATE = "2.5";
endmodule
(* blackbox *)
module EXTREFB (
input REFCLKP, REFCLKN,
output REFCLKO
);
parameter REFCK_PWDNB = "0b0";
parameter REFCK_RTERM = "0b0";
parameter REFCK_DCBIAS_EN = "0b0";
endmodule
(* blackbox *)
module PCSCLKDIV (
input CLKI, RST, SEL2, SEL1, SEL0,
output CDIV1, CDIVX
);
parameter GSR = "DISABLED";
endmodule

2
techlibs/ecp5/cells_sim.v
View File

@ -257,7 +257,7 @@ assign O = I;
endmodule endmodule
// --------------------------------------- // ---------------------------------------
(* keep *)
module TRELLIS_IO( module TRELLIS_IO(
inout B, inout B,
input I, input I,

1
techlibs/xilinx/cells_xtra.sh
View File

@ -112,6 +112,7 @@ function xtract_cell_decl()
xtract_cell_decl PHY_CONTROL xtract_cell_decl PHY_CONTROL
xtract_cell_decl PLLE2_ADV xtract_cell_decl PLLE2_ADV
xtract_cell_decl PLLE2_BASE xtract_cell_decl PLLE2_BASE
xtract_cell_decl PS7
xtract_cell_decl PULLDOWN xtract_cell_decl PULLDOWN
xtract_cell_decl PULLUP xtract_cell_decl PULLUP
# xtract_cell_decl RAM128X1D # xtract_cell_decl RAM128X1D

623
techlibs/xilinx/cells_xtra.v
View File

@ -3057,6 +3057,629 @@ module PLLE2_BASE (...);
input RST; input RST;
endmodule endmodule
module PS7 (...);
output DMA0DAVALID;
output DMA0DRREADY;
output DMA0RSTN;
output DMA1DAVALID;
output DMA1DRREADY;
output DMA1RSTN;
output DMA2DAVALID;
output DMA2DRREADY;
output DMA2RSTN;
output DMA3DAVALID;
output DMA3DRREADY;
output DMA3RSTN;
output EMIOCAN0PHYTX;
output EMIOCAN1PHYTX;
output EMIOENET0GMIITXEN;
output EMIOENET0GMIITXER;
output EMIOENET0MDIOMDC;
output EMIOENET0MDIOO;
output EMIOENET0MDIOTN;
output EMIOENET0PTPDELAYREQRX;
output EMIOENET0PTPDELAYREQTX;
output EMIOENET0PTPPDELAYREQRX;
output EMIOENET0PTPPDELAYREQTX;
output EMIOENET0PTPPDELAYRESPRX;
output EMIOENET0PTPPDELAYRESPTX;
output EMIOENET0PTPSYNCFRAMERX;
output EMIOENET0PTPSYNCFRAMETX;
output EMIOENET0SOFRX;
output EMIOENET0SOFTX;
output EMIOENET1GMIITXEN;
output EMIOENET1GMIITXER;
output EMIOENET1MDIOMDC;
output EMIOENET1MDIOO;
output EMIOENET1MDIOTN;
output EMIOENET1PTPDELAYREQRX;
output EMIOENET1PTPDELAYREQTX;
output EMIOENET1PTPPDELAYREQRX;
output EMIOENET1PTPPDELAYREQTX;
output EMIOENET1PTPPDELAYRESPRX;
output EMIOENET1PTPPDELAYRESPTX;
output EMIOENET1PTPSYNCFRAMERX;
output EMIOENET1PTPSYNCFRAMETX;
output EMIOENET1SOFRX;
output EMIOENET1SOFTX;
output EMIOI2C0SCLO;
output EMIOI2C0SCLTN;
output EMIOI2C0SDAO;
output EMIOI2C0SDATN;
output EMIOI2C1SCLO;
output EMIOI2C1SCLTN;
output EMIOI2C1SDAO;
output EMIOI2C1SDATN;
output EMIOPJTAGTDO;
output EMIOPJTAGTDTN;
output EMIOSDIO0BUSPOW;
output EMIOSDIO0CLK;
output EMIOSDIO0CMDO;
output EMIOSDIO0CMDTN;
output EMIOSDIO0LED;
output EMIOSDIO1BUSPOW;
output EMIOSDIO1CLK;
output EMIOSDIO1CMDO;
output EMIOSDIO1CMDTN;
output EMIOSDIO1LED;
output EMIOSPI0MO;
output EMIOSPI0MOTN;
output EMIOSPI0SCLKO;
output EMIOSPI0SCLKTN;
output EMIOSPI0SO;
output EMIOSPI0SSNTN;
output EMIOSPI0STN;
output EMIOSPI1MO;
output EMIOSPI1MOTN;
output EMIOSPI1SCLKO;
output EMIOSPI1SCLKTN;
output EMIOSPI1SO;
output EMIOSPI1SSNTN;
output EMIOSPI1STN;
output EMIOTRACECTL;
output EMIOUART0DTRN;
output EMIOUART0RTSN;
output EMIOUART0TX;
output EMIOUART1DTRN;
output EMIOUART1RTSN;
output EMIOUART1TX;
output EMIOUSB0VBUSPWRSELECT;
output EMIOUSB1VBUSPWRSELECT;
output EMIOWDTRSTO;
output EVENTEVENTO;
output MAXIGP0ARESETN;
output MAXIGP0ARVALID;
output MAXIGP0AWVALID;
output MAXIGP0BREADY;
output MAXIGP0RREADY;
output MAXIGP0WLAST;
output MAXIGP0WVALID;
output MAXIGP1ARESETN;
output MAXIGP1ARVALID;
output MAXIGP1AWVALID;
output MAXIGP1BREADY;
output MAXIGP1RREADY;
output MAXIGP1WLAST;
output MAXIGP1WVALID;
output SAXIACPARESETN;
output SAXIACPARREADY;
output SAXIACPAWREADY;
output SAXIACPBVALID;
output SAXIACPRLAST;
output SAXIACPRVALID;
output SAXIACPWREADY;
output SAXIGP0ARESETN;
output SAXIGP0ARREADY;
output SAXIGP0AWREADY;
output SAXIGP0BVALID;
output SAXIGP0RLAST;
output SAXIGP0RVALID;
output SAXIGP0WREADY;
output SAXIGP1ARESETN;
output SAXIGP1ARREADY;
output SAXIGP1AWREADY;
output SAXIGP1BVALID;
output SAXIGP1RLAST;
output SAXIGP1RVALID;
output SAXIGP1WREADY;
output SAXIHP0ARESETN;
output SAXIHP0ARREADY;
output SAXIHP0AWREADY;
output SAXIHP0BVALID;
output SAXIHP0RLAST;
output SAXIHP0RVALID;
output SAXIHP0WREADY;
output SAXIHP1ARESETN;
output SAXIHP1ARREADY;
output SAXIHP1AWREADY;
output SAXIHP1BVALID;
output SAXIHP1RLAST;
output SAXIHP1RVALID;
output SAXIHP1WREADY;
output SAXIHP2ARESETN;
output SAXIHP2ARREADY;
output SAXIHP2AWREADY;
output SAXIHP2BVALID;
output SAXIHP2RLAST;
output SAXIHP2RVALID;
output SAXIHP2WREADY;
output SAXIHP3ARESETN;
output SAXIHP3ARREADY;
output SAXIHP3AWREADY;
output SAXIHP3BVALID;
output SAXIHP3RLAST;
output SAXIHP3RVALID;
output SAXIHP3WREADY;
output [11:0] MAXIGP0ARID;
output [11:0] MAXIGP0AWID;
output [11:0] MAXIGP0WID;
output [11:0] MAXIGP1ARID;
output [11:0] MAXIGP1AWID;
output [11:0] MAXIGP1WID;
output [1:0] DMA0DATYPE;
output [1:0] DMA1DATYPE;
output [1:0] DMA2DATYPE;
output [1:0] DMA3DATYPE;
output [1:0] EMIOUSB0PORTINDCTL;
output [1:0] EMIOUSB1PORTINDCTL;
output [1:0] EVENTSTANDBYWFE;
output [1:0] EVENTSTANDBYWFI;
output [1:0] MAXIGP0ARBURST;
output [1:0] MAXIGP0ARLOCK;
output [1:0] MAXIGP0ARSIZE;
output [1:0] MAXIGP0AWBURST;
output [1:0] MAXIGP0AWLOCK;
output [1:0] MAXIGP0AWSIZE;
output [1:0] MAXIGP1ARBURST;
output [1:0] MAXIGP1ARLOCK;
output [1:0] MAXIGP1ARSIZE;
output [1:0] MAXIGP1AWBURST;
output [1:0] MAXIGP1AWLOCK;
output [1:0] MAXIGP1AWSIZE;
output [1:0] SAXIACPBRESP;
output [1:0] SAXIACPRRESP;
output [1:0] SAXIGP0BRESP;
output [1:0] SAXIGP0RRESP;
output [1:0] SAXIGP1BRESP;
output [1:0] SAXIGP1RRESP;
output [1:0] SAXIHP0BRESP;
output [1:0] SAXIHP0RRESP;
output [1:0] SAXIHP1BRESP;
output [1:0] SAXIHP1RRESP;
output [1:0] SAXIHP2BRESP;
output [1:0] SAXIHP2RRESP;
output [1:0] SAXIHP3BRESP;
output [1:0] SAXIHP3RRESP;
output [28:0] IRQP2F;
output [2:0] EMIOSDIO0BUSVOLT;
output [2:0] EMIOSDIO1BUSVOLT;
output [2:0] EMIOSPI0SSON;
output [2:0] EMIOSPI1SSON;
output [2:0] EMIOTTC0WAVEO;
output [2:0] EMIOTTC1WAVEO;
output [2:0] MAXIGP0ARPROT;
output [2:0] MAXIGP0AWPROT;
output [2:0] MAXIGP1ARPROT;
output [2:0] MAXIGP1AWPROT;
output [2:0] SAXIACPBID;
output [2:0] SAXIACPRID;
output [2:0] SAXIHP0RACOUNT;
output [2:0] SAXIHP1RACOUNT;
output [2:0] SAXIHP2RACOUNT;
output [2:0] SAXIHP3RACOUNT;
output [31:0] EMIOTRACEDATA;
output [31:0] FTMTP2FDEBUG;
output [31:0] MAXIGP0ARADDR;
output [31:0] MAXIGP0AWADDR;
output [31:0] MAXIGP0WDATA;
output [31:0] MAXIGP1ARADDR;
output [31:0] MAXIGP1AWADDR;
output [31:0] MAXIGP1WDATA;
output [31:0] SAXIGP0RDATA;
output [31:0] SAXIGP1RDATA;
output [3:0] EMIOSDIO0DATAO;
output [3:0] EMIOSDIO0DATATN;
output [3:0] EMIOSDIO1DATAO;
output [3:0] EMIOSDIO1DATATN;
output [3:0] FCLKCLK;
output [3:0] FCLKRESETN;
output [3:0] FTMTF2PTRIGACK;
output [3:0] FTMTP2FTRIG;
output [3:0] MAXIGP0ARCACHE;
output [3:0] MAXIGP0ARLEN;
output [3:0] MAXIGP0ARQOS;
output [3:0] MAXIGP0AWCACHE;
output [3:0] MAXIGP0AWLEN;
output [3:0] MAXIGP0AWQOS;
output [3:0] MAXIGP0WSTRB;
output [3:0] MAXIGP1ARCACHE;
output [3:0] MAXIGP1ARLEN;
output [3:0] MAXIGP1ARQOS;
output [3:0] MAXIGP1AWCACHE;
output [3:0] MAXIGP1AWLEN;
output [3:0] MAXIGP1AWQOS;
output [3:0] MAXIGP1WSTRB;
output [5:0] SAXIGP0BID;
output [5:0] SAXIGP0RID;
output [5:0] SAXIGP1BID;
output [5:0] SAXIGP1RID;
output [5:0] SAXIHP0BID;
output [5:0] SAXIHP0RID;
output [5:0] SAXIHP0WACOUNT;
output [5:0] SAXIHP1BID;
output [5:0] SAXIHP1RID;
output [5:0] SAXIHP1WACOUNT;
output [5:0] SAXIHP2BID;
output [5:0] SAXIHP2RID;
output [5:0] SAXIHP2WACOUNT;
output [5:0] SAXIHP3BID;
output [5:0] SAXIHP3RID;
output [5:0] SAXIHP3WACOUNT;
output [63:0] EMIOGPIOO;
output [63:0] EMIOGPIOTN;
output [63:0] SAXIACPRDATA;
output [63:0] SAXIHP0RDATA;
output [63:0] SAXIHP1RDATA;
output [63:0] SAXIHP2RDATA;
output [63:0] SAXIHP3RDATA;
output [7:0] EMIOENET0GMIITXD;
output [7:0] EMIOENET1GMIITXD;
output [7:0] SAXIHP0RCOUNT;
output [7:0] SAXIHP0WCOUNT;
output [7:0] SAXIHP1RCOUNT;
output [7:0] SAXIHP1WCOUNT;
output [7:0] SAXIHP2RCOUNT;
output [7:0] SAXIHP2WCOUNT;
output [7:0] SAXIHP3RCOUNT;
output [7:0] SAXIHP3WCOUNT;
inout DDRCASB;
inout DDRCKE;
inout DDRCKN;
inout DDRCKP;
inout DDRCSB;
inout DDRDRSTB;
inout DDRODT;
inout DDRRASB;
inout DDRVRN;
inout DDRVRP;
inout DDRWEB;
inout PSCLK;
inout PSPORB;
inout PSSRSTB;
inout [14:0] DDRA;
inout [2:0] DDRBA;
inout [31:0] DDRDQ;
inout [3:0] DDRDM;
inout [3:0] DDRDQSN;
inout [3:0] DDRDQSP;
inout [53:0] MIO;
input DMA0ACLK;
input DMA0DAREADY;
input DMA0DRLAST;
input DMA0DRVALID;
input DMA1ACLK;
input DMA1DAREADY;
input DMA1DRLAST;
input DMA1DRVALID;
input DMA2ACLK;
input DMA2DAREADY;
input DMA2DRLAST;
input DMA2DRVALID;
input DMA3ACLK;
input DMA3DAREADY;
input DMA3DRLAST;
input DMA3DRVALID;
input EMIOCAN0PHYRX;
input EMIOCAN1PHYRX;
input EMIOENET0EXTINTIN;
input EMIOENET0GMIICOL;
input EMIOENET0GMIICRS;
input EMIOENET0GMIIRXCLK;
input EMIOENET0GMIIRXDV;
input EMIOENET0GMIIRXER;
input EMIOENET0GMIITXCLK;
input EMIOENET0MDIOI;
input EMIOENET1EXTINTIN;
input EMIOENET1GMIICOL;
input EMIOENET1GMIICRS;
input EMIOENET1GMIIRXCLK;
input EMIOENET1GMIIRXDV;
input EMIOENET1GMIIRXER;
input EMIOENET1GMIITXCLK;
input EMIOENET1MDIOI;
input EMIOI2C0SCLI;
input EMIOI2C0SDAI;
input EMIOI2C1SCLI;
input EMIOI2C1SDAI;
input EMIOPJTAGTCK;
input EMIOPJTAGTDI;
input EMIOPJTAGTMS;
input EMIOSDIO0CDN;
input EMIOSDIO0CLKFB;
input EMIOSDIO0CMDI;
input EMIOSDIO0WP;
input EMIOSDIO1CDN;
input EMIOSDIO1CLKFB;
input EMIOSDIO1CMDI;
input EMIOSDIO1WP;
input EMIOSPI0MI;
input EMIOSPI0SCLKI;
input EMIOSPI0SI;
input EMIOSPI0SSIN;
input EMIOSPI1MI;
input EMIOSPI1SCLKI;
input EMIOSPI1SI;
input EMIOSPI1SSIN;
input EMIOSRAMINTIN;
input EMIOTRACECLK;
input EMIOUART0CTSN;
input EMIOUART0DCDN;
input EMIOUART0DSRN;
input EMIOUART0RIN;
input EMIOUART0RX;
input EMIOUART1CTSN;
input EMIOUART1DCDN;
input EMIOUART1DSRN;
input EMIOUART1RIN;
input EMIOUART1RX;
input EMIOUSB0VBUSPWRFAULT;
input EMIOUSB1VBUSPWRFAULT;
input EMIOWDTCLKI;
input EVENTEVENTI;
input FPGAIDLEN;
input FTMDTRACEINCLOCK;
input FTMDTRACEINVALID;
input MAXIGP0ACLK;
input MAXIGP0ARREADY;
input MAXIGP0AWREADY;
input MAXIGP0BVALID;
input MAXIGP0RLAST;
input MAXIGP0RVALID;
input MAXIGP0WREADY;
input MAXIGP1ACLK;
input MAXIGP1ARREADY;
input MAXIGP1AWREADY;
input MAXIGP1BVALID;
input MAXIGP1RLAST;
input MAXIGP1RVALID;
input MAXIGP1WREADY;
input SAXIACPACLK;
input SAXIACPARVALID;
input SAXIACPAWVALID;
input SAXIACPBREADY;
input SAXIACPRREADY;
input SAXIACPWLAST;
input SAXIACPWVALID;
input SAXIGP0ACLK;
input SAXIGP0ARVALID;
input SAXIGP0AWVALID;
input SAXIGP0BREADY;
input SAXIGP0RREADY;
input SAXIGP0WLAST;
input SAXIGP0WVALID;
input SAXIGP1ACLK;
input SAXIGP1ARVALID;
input SAXIGP1AWVALID;
input SAXIGP1BREADY;
input SAXIGP1RREADY;
input SAXIGP1WLAST;
input SAXIGP1WVALID;
input SAXIHP0ACLK;
input SAXIHP0ARVALID;
input SAXIHP0AWVALID;
input SAXIHP0BREADY;
input SAXIHP0RDISSUECAP1EN;
input SAXIHP0RREADY;
input SAXIHP0WLAST;
input SAXIHP0WRISSUECAP1EN;
input SAXIHP0WVALID;
input SAXIHP1ACLK;
input SAXIHP1ARVALID;
input SAXIHP1AWVALID;
input SAXIHP1BREADY;
input SAXIHP1RDISSUECAP1EN;
input SAXIHP1RREADY;
input SAXIHP1WLAST;
input SAXIHP1WRISSUECAP1EN;
input SAXIHP1WVALID;
input SAXIHP2ACLK;
input SAXIHP2ARVALID;
input SAXIHP2AWVALID;
input SAXIHP2BREADY;
input SAXIHP2RDISSUECAP1EN;
input SAXIHP2RREADY;
input SAXIHP2WLAST;
input SAXIHP2WRISSUECAP1EN;
input SAXIHP2WVALID;
input SAXIHP3ACLK;
input SAXIHP3ARVALID;
input SAXIHP3AWVALID;
input SAXIHP3BREADY;
input SAXIHP3RDISSUECAP1EN;
input SAXIHP3RREADY;
input SAXIHP3WLAST;
input SAXIHP3WRISSUECAP1EN;
input SAXIHP3WVALID;
input [11:0] MAXIGP0BID;
input [11:0] MAXIGP0RID;
input [11:0] MAXIGP1BID;
input [11:0] MAXIGP1RID;
input [19:0] IRQF2P;
input [1:0] DMA0DRTYPE;
input [1:0] DMA1DRTYPE;
input [1:0] DMA2DRTYPE;
input [1:0] DMA3DRTYPE;
input [1:0] MAXIGP0BRESP;
input [1:0] MAXIGP0RRESP;
input [1:0] MAXIGP1BRESP;
input [1:0] MAXIGP1RRESP;
input [1:0] SAXIACPARBURST;
input [1:0] SAXIACPARLOCK;
input [1:0] SAXIACPARSIZE;
input [1:0] SAXIACPAWBURST;
input [1:0] SAXIACPAWLOCK;
input [1:0] SAXIACPAWSIZE;
input [1:0] SAXIGP0ARBURST;
input [1:0] SAXIGP0ARLOCK;
input [1:0] SAXIGP0ARSIZE;
input [1:0] SAXIGP0AWBURST;
input [1:0] SAXIGP0AWLOCK;
input [1:0] SAXIGP0AWSIZE;
input [1:0] SAXIGP1ARBURST;
input [1:0] SAXIGP1ARLOCK;
input [1:0] SAXIGP1ARSIZE;
input [1:0] SAXIGP1AWBURST;
input [1:0] SAXIGP1AWLOCK;
input [1:0] SAXIGP1AWSIZE;
input [1:0] SAXIHP0ARBURST;
input [1:0] SAXIHP0ARLOCK;
input [1:0] SAXIHP0ARSIZE;
input [1:0] SAXIHP0AWBURST;
input [1:0] SAXIHP0AWLOCK;
input [1:0] SAXIHP0AWSIZE;
input [1:0] SAXIHP1ARBURST;
input [1:0] SAXIHP1ARLOCK;
input [1:0] SAXIHP1ARSIZE;
input [1:0] SAXIHP1AWBURST;
input [1:0] SAXIHP1AWLOCK;
input [1:0] SAXIHP1AWSIZE;
input [1:0] SAXIHP2ARBURST;
input [1:0] SAXIHP2ARLOCK;
input [1:0] SAXIHP2ARSIZE;
input [1:0] SAXIHP2AWBURST;
input [1:0] SAXIHP2AWLOCK;
input [1:0] SAXIHP2AWSIZE;
input [1:0] SAXIHP3ARBURST;
input [1:0] SAXIHP3ARLOCK;
input [1:0] SAXIHP3ARSIZE;
input [1:0] SAXIHP3AWBURST;
input [1:0] SAXIHP3AWLOCK;
input [1:0] SAXIHP3AWSIZE;
input [2:0] EMIOTTC0CLKI;
input [2:0] EMIOTTC1CLKI;
input [2:0] SAXIACPARID;
input [2:0] SAXIACPARPROT;
input [2:0] SAXIACPAWID;
input [2:0] SAXIACPAWPROT;
input [2:0] SAXIACPWID;
input [2:0] SAXIGP0ARPROT;
input [2:0] SAXIGP0AWPROT;
input [2:0] SAXIGP1ARPROT;
input [2:0] SAXIGP1AWPROT;
input [2:0] SAXIHP0ARPROT;
input [2:0] SAXIHP0AWPROT;
input [2:0] SAXIHP1ARPROT;
input [2:0] SAXIHP1AWPROT;
input [2:0] SAXIHP2ARPROT;
input [2:0] SAXIHP2AWPROT;
input [2:0] SAXIHP3ARPROT;
input [2:0] SAXIHP3AWPROT;
input [31:0] FTMDTRACEINDATA;
input [31:0] FTMTF2PDEBUG;
input [31:0] MAXIGP0RDATA;
input [31:0] MAXIGP1RDATA;
input [31:0] SAXIACPARADDR;
input [31:0] SAXIACPAWADDR;
input [31:0] SAXIGP0ARADDR;
input [31:0] SAXIGP0AWADDR;
input [31:0] SAXIGP0WDATA;
input [31:0] SAXIGP1ARADDR;
input [31:0] SAXIGP1AWADDR;
input [31:0] SAXIGP1WDATA;
input [31:0] SAXIHP0ARADDR;
input [31:0] SAXIHP0AWADDR;
input [31:0] SAXIHP1ARADDR;
input [31:0] SAXIHP1AWADDR;
input [31:0] SAXIHP2ARADDR;
input [31:0] SAXIHP2AWADDR;
input [31:0] SAXIHP3ARADDR;
input [31:0] SAXIHP3AWADDR;
input [3:0] DDRARB;
input [3:0] EMIOSDIO0DATAI;
input [3:0] EMIOSDIO1DATAI;
input [3:0] FCLKCLKTRIGN;
input [3:0] FTMDTRACEINATID;
input [3:0] FTMTF2PTRIG;
input [3:0] FTMTP2FTRIGACK;
input [3:0] SAXIACPARCACHE;
input [3:0] SAXIACPARLEN;
input [3:0] SAXIACPARQOS;
input [3:0] SAXIACPAWCACHE;
input [3:0] SAXIACPAWLEN;
input [3:0] SAXIACPAWQOS;
input [3:0] SAXIGP0ARCACHE;
input [3:0] SAXIGP0ARLEN;
input [3:0] SAXIGP0ARQOS;
input [3:0] SAXIGP0AWCACHE;
input [3:0] SAXIGP0AWLEN;
input [3:0] SAXIGP0AWQOS;
input [3:0] SAXIGP0WSTRB;
input [3:0] SAXIGP1ARCACHE;
input [3:0] SAXIGP1ARLEN;
input [3:0] SAXIGP1ARQOS;
input [3:0] SAXIGP1AWCACHE;
input [3:0] SAXIGP1AWLEN;
input [3:0] SAXIGP1AWQOS;
input [3:0] SAXIGP1WSTRB;
input [3:0] SAXIHP0ARCACHE;
input [3:0] SAXIHP0ARLEN;
input [3:0] SAXIHP0ARQOS;
input [3:0] SAXIHP0AWCACHE;
input [3:0] SAXIHP0AWLEN;
input [3:0] SAXIHP0AWQOS;
input [3:0] SAXIHP1ARCACHE;
input [3:0] SAXIHP1ARLEN;
input [3:0] SAXIHP1ARQOS;
input [3:0] SAXIHP1AWCACHE;
input [3:0] SAXIHP1AWLEN;
input [3:0] SAXIHP1AWQOS;
input [3:0] SAXIHP2ARCACHE;
input [3:0] SAXIHP2ARLEN;
input [3:0] SAXIHP2ARQOS;
input [3:0] SAXIHP2AWCACHE;
input [3:0] SAXIHP2AWLEN;
input [3:0] SAXIHP2AWQOS;
input [3:0] SAXIHP3ARCACHE;
input [3:0] SAXIHP3ARLEN;
input [3:0] SAXIHP3ARQOS;
input [3:0] SAXIHP3AWCACHE;
input [3:0] SAXIHP3AWLEN;
input [3:0] SAXIHP3AWQOS;
input [4:0] SAXIACPARUSER;
input [4:0] SAXIACPAWUSER;
input [5:0] SAXIGP0ARID;
input [5:0] SAXIGP0AWID;
input [5:0] SAXIGP0WID;
input [5:0] SAXIGP1ARID;
input [5:0] SAXIGP1AWID;
input [5:0] SAXIGP1WID;
input [5:0] SAXIHP0ARID;
input [5:0] SAXIHP0AWID;
input [5:0] SAXIHP0WID;
input [5:0] SAXIHP1ARID;
input [5:0] SAXIHP1AWID;
input [5:0] SAXIHP1WID;
input [5:0] SAXIHP2ARID;
input [5:0] SAXIHP2AWID;
input [5:0] SAXIHP2WID;
input [5:0] SAXIHP3ARID;
input [5:0] SAXIHP3AWID;
input [5:0] SAXIHP3WID;
input [63:0] EMIOGPIOI;
input [63:0] SAXIACPWDATA;
input [63:0] SAXIHP0WDATA;
input [63:0] SAXIHP1WDATA;
input [63:0] SAXIHP2WDATA;
input [63:0] SAXIHP3WDATA;
input [7:0] EMIOENET0GMIIRXD;
input [7:0] EMIOENET1GMIIRXD;
input [7:0] SAXIACPWSTRB;
input [7:0] SAXIHP0WSTRB;
input [7:0] SAXIHP1WSTRB;
input [7:0] SAXIHP2WSTRB;
input [7:0] SAXIHP3WSTRB;
endmodule
module PULLDOWN (...); module PULLDOWN (...);
output O; output O;
endmodule endmodule