riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix iopadmap for cases where IO pins already have buffers on them 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-05-15 13:13:43 +02:00
parent 0fad1570b5
commit edd297fb1c
1 changed files with 35 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
passes/techmap/iopadmap.cc
View File

@ -146,10 +146,34 @@ struct IopadmapPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
dict<IdString, pool<int>> skip_wires; dict<IdString, pool<int>> skip_wires;
pool<SigBit> skip_wire_bits;
SigMap sigmap(module);
for (auto cell : module->cells())
{
if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2)))
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2))))
skip_wire_bits.insert(bit);
if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2)))
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2))))
skip_wire_bits.insert(bit);
if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2)))
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2))))
skip_wire_bits.insert(bit);
if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3)))
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3))))
skip_wire_bits.insert(bit);
if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4)))
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4))))
skip_wire_bits.insert(bit);
}
if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty()) if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
{ {
SigMap sigmap(module);
dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits; dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
for (auto cell : module->cells()) for (auto cell : module->cells())
@ -177,6 +201,9 @@ struct IopadmapPass : public Pass {
if (tbuf_bits.count(mapped_wire_bit) == 0) if (tbuf_bits.count(mapped_wire_bit) == 0)
continue; continue;
if (skip_wire_bits.count(mapped_wire_bit))
continue;
auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit); auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
Cell *tbuf_cell = module->cell(tbuf_cache.first); Cell *tbuf_cell = module->cell(tbuf_cache.first);
@ -272,6 +299,13 @@ struct IopadmapPass : public Pass {
skip_bit_indices = skip_wires.at(wire->name); skip_bit_indices = skip_wires.at(wire->name);
} }
for (int i = 0; i < GetSize(wire); i++)
if (skip_wire_bits.count(sigmap(SigBit(wire, i))))
skip_bit_indices.insert(i);
if (GetSize(wire) == GetSize(skip_bit_indices))
continue;
if (wire->port_input && !wire->port_output) { if (wire->port_input && !wire->port_output) {
if (inpad_celltype.empty()) { if (inpad_celltype.empty()) {
log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));