mirror of https://github.com/YosysHQ/yosys.git
Added is_signed argument to SigSpec.as_int() and Const.as_int()
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@ -92,12 +92,15 @@ bool RTLIL::Const::as_bool() const
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return false;
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return false;
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}
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}
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int RTLIL::Const::as_int() const
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int RTLIL::Const::as_int(bool is_signed) const
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{
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{
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int ret = 0;
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int32_t ret = 0;
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for (size_t i = 0; i < bits.size() && i < 32; i++)
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for (size_t i = 0; i < bits.size() && i < 32; i++)
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if (bits[i] == RTLIL::S1)
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if (bits[i] == RTLIL::S1)
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ret |= 1 << i;
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ret |= 1 << i;
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if (is_signed && bits.back() == RTLIL::S1)
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for (size_t i = bits.size(); i < 32; i++)
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ret |= 1 << i;
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return ret;
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return ret;
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}
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}
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@ -2647,14 +2650,14 @@ bool RTLIL::SigSpec::as_bool() const
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return false;
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return false;
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}
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}
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int RTLIL::SigSpec::as_int() const
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int RTLIL::SigSpec::as_int(bool is_signed) const
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{
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{
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cover("kernel.rtlil.sigspec.as_int");
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cover("kernel.rtlil.sigspec.as_int");
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pack();
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pack();
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log_assert(is_fully_const() && SIZE(chunks_) <= 1);
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log_assert(is_fully_const() && SIZE(chunks_) <= 1);
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if (width_)
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if (width_)
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return chunks_[0].data.as_int();
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return chunks_[0].data.as_int(is_signed);
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return 0;
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return 0;
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}
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}
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@ -436,7 +436,7 @@ struct RTLIL::Const
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bool operator !=(const RTLIL::Const &other) const;
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bool operator !=(const RTLIL::Const &other) const;
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bool as_bool() const;
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bool as_bool() const;
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int as_int() const;
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int as_int(bool is_signed = false) const;
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std::string as_string() const;
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std::string as_string() const;
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std::string decode_string() const;
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std::string decode_string() const;
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@ -1038,7 +1038,7 @@ public:
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bool has_marked_bits() const;
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bool has_marked_bits() const;
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bool as_bool() const;
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bool as_bool() const;
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int as_int() const;
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int as_int(bool is_signed = false) const;
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std::string as_string() const;
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std::string as_string() const;
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RTLIL::Const as_const() const;
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RTLIL::Const as_const() const;
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RTLIL::Wire *as_wire() const;
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RTLIL::Wire *as_wire() const;
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