riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added dump -m and -n options

This commit is contained in:
Clifford Wolf 2013-11-29 10:33:36 +01:00
parent f89ecbc100
commit ed441346ca
2 changed files with 89 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
backends/ilang/ilang_backend.cc
View File

@ -258,8 +258,13 @@ void ILANG_BACKEND::dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec
fprintf(f, "\n");
}
void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module *module, const RTLIL::Design *design, bool only_selected)
void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module *module, const RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
{
bool print_header = flag_m || design->selected_whole_module(module->name);
bool print_body = !flag_n || !design->selected_whole_module(module->name);
if (print_header)
{
for (auto it = module->attributes.begin(); it != module->attributes.end(); it++) {
fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
dump_const(f, it->second);
@ -267,7 +272,10 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module
}
fprintf(f, "%s" "module %s\n", indent.c_str(), module->name.c_str());
}
if (print_body)
{
for (auto it = module->wires.begin(); it != module->wires.end(); it++)
if (!only_selected || design->selected(module, it->second)) {
if (only_selected)
@ -315,17 +323,28 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module
first_conn_line = false;
}
}
}
if (print_header)
fprintf(f, "%s" "end\n", indent.c_str());
}
void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_selected)
void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
{
if (!flag_m) {
int count_selected_mods = 0;
for (auto it = design->modules.begin(); it != design->modules.end(); it++)
if (design->selected(it->second))
count_selected_mods++;
if (count_selected_mods > 1)
flag_m = true;
}
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if (!only_selected || design->selected(it->second)) {
if (only_selected)
fprintf(f, "\n");
dump_module(f, "", it->second, design, only_selected);
dump_module(f, "", it->second, design, only_selected, flag_m, flag_n);
}
}
}
@ -364,7 +383,7 @@ struct IlangBackend : public Backend {
log("Output filename: %s\n", filename.c_str());
fprintf(f, "# Generated by %s\n", yosys_version_str);
ILANG_BACKEND::dump_design(f, design, selected);
ILANG_BACKEND::dump_design(f, design, selected, true, false);
}
} IlangBackend;
@ -379,6 +398,13 @@ struct DumpPass : public Pass {
log("Write the selected parts of the design to the console or specified file in\n");
log("ilang format.\n");
log("\n");
log(" -m\n");
log(" also dump the module headers, even if only parts of a single");
log(" module is selected\n");
log("\n");
log(" -n\n");
log(" only dump the module headers if the entire module is selected\n");
log("\n");
log(" -outfile <filename>\n");
log(" Write to the specified file.\n");
log("\n");
@ -386,6 +412,7 @@ struct DumpPass : public Pass {
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
std::string filename;
bool flag_m = false, flag_n = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -395,6 +422,14 @@ struct DumpPass : public Pass {
filename = args[++argidx];
continue;
}
if (arg == "-m") {
flag_m = true;
continue;
}
if (arg == "-n") {
flag_n = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -411,7 +446,7 @@ struct DumpPass : public Pass {
f = open_memstream(&buf_ptr, &buf_size);
}
ILANG_BACKEND::dump_design(f, design, true);
ILANG_BACKEND::dump_design(f, design, true, flag_m, flag_n);
fclose(f);

4
backends/ilang/ilang_backend.h
View File

@ -40,8 +40,8 @@ namespace ILANG_BACKEND {
void dump_proc_sync(FILE *f, std::string indent, const RTLIL::SyncRule *sy);
void dump_proc(FILE *f, std::string indent, const RTLIL::Process *proc);
void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right);
void dump_module(FILE *f, std::string indent, const RTLIL::Module *module, const RTLIL::Design *design, bool only_selected);
void dump_design(FILE *f, const RTLIL::Design *design, bool only_selected);
void dump_module(FILE *f, std::string indent, const RTLIL::Module *module, const RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false);
void dump_design(FILE *f, const RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false);
}
#endif