mirror of https://github.com/YosysHQ/yosys.git
Added dump -m and -n options
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parent
f89ecbc100
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ed441346ca
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@ -258,74 +258,93 @@ void ILANG_BACKEND::dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec
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fprintf(f, "\n");
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fprintf(f, "\n");
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}
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}
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void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module *module, const RTLIL::Design *design, bool only_selected)
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void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module *module, const RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
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{
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{
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for (auto it = module->attributes.begin(); it != module->attributes.end(); it++) {
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bool print_header = flag_m || design->selected_whole_module(module->name);
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fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
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bool print_body = !flag_n || !design->selected_whole_module(module->name);
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dump_const(f, it->second);
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fprintf(f, "\n");
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if (print_header)
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{
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for (auto it = module->attributes.begin(); it != module->attributes.end(); it++) {
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fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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fprintf(f, "\n");
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}
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fprintf(f, "%s" "module %s\n", indent.c_str(), module->name.c_str());
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}
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}
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fprintf(f, "%s" "module %s\n", indent.c_str(), module->name.c_str());
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if (print_body)
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{
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for (auto it = module->wires.begin(); it != module->wires.end(); it++)
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if (!only_selected || design->selected(module, it->second)) {
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if (only_selected)
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fprintf(f, "\n");
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dump_wire(f, indent + " ", it->second);
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}
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for (auto it = module->wires.begin(); it != module->wires.end(); it++)
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for (auto it = module->memories.begin(); it != module->memories.end(); it++)
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if (!only_selected || design->selected(module, it->second)) {
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if (!only_selected || design->selected(module, it->second)) {
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if (only_selected)
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if (only_selected)
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fprintf(f, "\n");
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fprintf(f, "\n");
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dump_wire(f, indent + " ", it->second);
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dump_memory(f, indent + " ", it->second);
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}
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}
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for (auto it = module->memories.begin(); it != module->memories.end(); it++)
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for (auto it = module->cells.begin(); it != module->cells.end(); it++)
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if (!only_selected || design->selected(module, it->second)) {
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if (!only_selected || design->selected(module, it->second)) {
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if (only_selected)
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if (only_selected)
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fprintf(f, "\n");
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fprintf(f, "\n");
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dump_memory(f, indent + " ", it->second);
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dump_cell(f, indent + " ", it->second);
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}
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}
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for (auto it = module->cells.begin(); it != module->cells.end(); it++)
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for (auto it = module->processes.begin(); it != module->processes.end(); it++)
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if (!only_selected || design->selected(module, it->second)) {
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if (!only_selected || design->selected(module, it->second)) {
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if (only_selected)
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if (only_selected)
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fprintf(f, "\n");
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fprintf(f, "\n");
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dump_cell(f, indent + " ", it->second);
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dump_proc(f, indent + " ", it->second);
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}
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}
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for (auto it = module->processes.begin(); it != module->processes.end(); it++)
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bool first_conn_line = true;
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if (!only_selected || design->selected(module, it->second)) {
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for (auto it = module->connections.begin(); it != module->connections.end(); it++) {
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if (only_selected)
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bool show_conn = !only_selected;
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fprintf(f, "\n");
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if (only_selected) {
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dump_proc(f, indent + " ", it->second);
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RTLIL::SigSpec sigs = it->first;
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}
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sigs.append(it->second);
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for (auto &c : sigs.chunks) {
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bool first_conn_line = true;
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if (c.wire == NULL || !design->selected(module, c.wire))
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for (auto it = module->connections.begin(); it != module->connections.end(); it++) {
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continue;
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bool show_conn = !only_selected;
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show_conn = true;
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if (only_selected) {
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}
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RTLIL::SigSpec sigs = it->first;
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}
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sigs.append(it->second);
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if (show_conn) {
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for (auto &c : sigs.chunks) {
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if (only_selected && first_conn_line)
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if (c.wire == NULL || !design->selected(module, c.wire))
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fprintf(f, "\n");
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continue;
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dump_conn(f, indent + " ", it->first, it->second);
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show_conn = true;
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first_conn_line = false;
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}
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}
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}
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}
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if (show_conn) {
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if (only_selected && first_conn_line)
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fprintf(f, "\n");
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dump_conn(f, indent + " ", it->first, it->second);
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first_conn_line = false;
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}
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}
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}
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fprintf(f, "%s" "end\n", indent.c_str());
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if (print_header)
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fprintf(f, "%s" "end\n", indent.c_str());
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}
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}
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void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_selected)
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void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
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{
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{
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if (!flag_m) {
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int count_selected_mods = 0;
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for (auto it = design->modules.begin(); it != design->modules.end(); it++)
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if (design->selected(it->second))
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count_selected_mods++;
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if (count_selected_mods > 1)
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flag_m = true;
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}
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for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
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for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
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if (!only_selected || design->selected(it->second)) {
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if (!only_selected || design->selected(it->second)) {
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if (only_selected)
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if (only_selected)
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fprintf(f, "\n");
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fprintf(f, "\n");
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dump_module(f, "", it->second, design, only_selected);
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dump_module(f, "", it->second, design, only_selected, flag_m, flag_n);
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}
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}
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}
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}
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}
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}
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@ -364,7 +383,7 @@ struct IlangBackend : public Backend {
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log("Output filename: %s\n", filename.c_str());
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log("Output filename: %s\n", filename.c_str());
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fprintf(f, "# Generated by %s\n", yosys_version_str);
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fprintf(f, "# Generated by %s\n", yosys_version_str);
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ILANG_BACKEND::dump_design(f, design, selected);
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ILANG_BACKEND::dump_design(f, design, selected, true, false);
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}
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}
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} IlangBackend;
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} IlangBackend;
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@ -379,6 +398,13 @@ struct DumpPass : public Pass {
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log("Write the selected parts of the design to the console or specified file in\n");
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log("Write the selected parts of the design to the console or specified file in\n");
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log("ilang format.\n");
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log("ilang format.\n");
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log("\n");
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log("\n");
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log(" -m\n");
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log(" also dump the module headers, even if only parts of a single");
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log(" module is selected\n");
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log("\n");
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log(" -n\n");
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log(" only dump the module headers if the entire module is selected\n");
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log("\n");
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log(" -outfile <filename>\n");
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log(" -outfile <filename>\n");
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log(" Write to the specified file.\n");
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log(" Write to the specified file.\n");
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log("\n");
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log("\n");
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@ -386,6 +412,7 @@ struct DumpPass : public Pass {
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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{
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std::string filename;
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std::string filename;
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bool flag_m = false, flag_n = false;
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size_t argidx;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -395,6 +422,14 @@ struct DumpPass : public Pass {
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filename = args[++argidx];
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filename = args[++argidx];
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continue;
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continue;
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}
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}
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if (arg == "-m") {
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flag_m = true;
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continue;
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}
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if (arg == "-n") {
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flag_n = true;
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continue;
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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@ -411,7 +446,7 @@ struct DumpPass : public Pass {
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f = open_memstream(&buf_ptr, &buf_size);
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f = open_memstream(&buf_ptr, &buf_size);
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}
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}
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ILANG_BACKEND::dump_design(f, design, true);
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ILANG_BACKEND::dump_design(f, design, true, flag_m, flag_n);
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fclose(f);
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fclose(f);
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@ -40,8 +40,8 @@ namespace ILANG_BACKEND {
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void dump_proc_sync(FILE *f, std::string indent, const RTLIL::SyncRule *sy);
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void dump_proc_sync(FILE *f, std::string indent, const RTLIL::SyncRule *sy);
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void dump_proc(FILE *f, std::string indent, const RTLIL::Process *proc);
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void dump_proc(FILE *f, std::string indent, const RTLIL::Process *proc);
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void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right);
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void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right);
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void dump_module(FILE *f, std::string indent, const RTLIL::Module *module, const RTLIL::Design *design, bool only_selected);
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void dump_module(FILE *f, std::string indent, const RTLIL::Module *module, const RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false);
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void dump_design(FILE *f, const RTLIL::Design *design, bool only_selected);
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void dump_design(FILE *f, const RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false);
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}
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}
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#endif
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#endif
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