mirror of https://github.com/YosysHQ/yosys.git
Fix wire numbering
This commit is contained in:
parent
43cd047fb9
commit
ece5c3ab38
|
@ -589,11 +589,12 @@ struct XAigerWriter
|
||||||
if (cell->input(c.first)) {
|
if (cell->input(c.first)) {
|
||||||
box_inputs += c.second.size();
|
box_inputs += c.second.size();
|
||||||
if (holes_cell) {
|
if (holes_cell) {
|
||||||
holes_wire = holes_module->wire(stringf("\\i%d", num_inputs++));
|
holes_wire = holes_module->wire(stringf("\\i%d", num_inputs));
|
||||||
if (!holes_wire) {
|
if (!holes_wire) {
|
||||||
holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
|
holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
|
||||||
holes_wire->port_input = true;
|
holes_wire->port_input = true;
|
||||||
}
|
}
|
||||||
|
++num_inputs;
|
||||||
holes_cell->setPort(c.first, holes_wire);
|
holes_cell->setPort(c.first, holes_wire);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue