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Improved ice40_ffinit

This commit is contained in:
Clifford Wolf 2015-12-22 11:15:25 +01:00
parent f1b959dc69
commit ec93d258a4
1 changed files with 22 additions and 1 deletions
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23
techlibs/ice40/ice40_ffinit.cc
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@ -86,9 +86,15 @@ struct Ice40FfinitPass : public Pass {
}
}
pool<IdString> sb_dff_types = {
"\\SB_DFF", "\\SB_DFFE", "\\SB_DFFSR", "\\SB_DFFR", "\\SB_DFFSS", "\\SB_DFFS", "\\SB_DFFESR",
"\\SB_DFFER", "\\SB_DFFESS", "\\SB_DFFES", "\\SB_DFFN", "\\SB_DFFNE", "\\SB_DFFNSR", "\\SB_DFFNR",
"\\SB_DFFNSS", "\\SB_DFFNS", "\\SB_DFFNESR", "\\SB_DFFNER", "\\SB_DFFNESS", "\\SB_DFFNES"
};
for (auto cell : module->selected_cells())
{
if (!cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFN", "\\SB_DFFNE"))
if (!sb_dff_types.count(cell->type))
continue;
SigBit sig_d = sigmap(cell->getPort("\\D"));
@ -106,6 +112,21 @@ struct Ice40FfinitPass : public Pass {
if (val == State::S0)
continue;
string type_str = cell->type.str();
if (type_str.back() == 'S') {
type_str.back() = 'R';
cell->type = type_str;
cell->setPort("\\R", cell->getPort("\\S"));
cell->unsetPort("\\S");
} else
if (type_str.back() == 'R') {
type_str.back() = 'S';
cell->type = type_str;
cell->setPort("\\S", cell->getPort("\\R"));
cell->unsetPort("\\R");
}
Wire *new_sig_d = module->addWire(NEW_ID);
Wire *new_sig_q = module->addWire(NEW_ID);