riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

abc9_ops -prep_hier to unmap entire module

This commit is contained in:
Eddie Hung 2023-05-21 18:20:18 -07:00 committed by Lofty
parent 862631d657
commit ec8d7b1c68
1 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
passes/techmap/abc9_ops.cc
View File

@ -233,22 +233,23 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
if (derived_type != cell->type) { if (derived_type != cell->type) {
auto unmap_module = unmap_design->addModule(derived_type); auto unmap_module = unmap_design->addModule(derived_type);
auto replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
for (auto port : derived_module->ports) { for (auto port : derived_module->ports) {
auto w = unmap_module->addWire(port, derived_module->wire(port)); auto w = unmap_module->addWire(port, derived_module->wire(port));
// Do not propagate (* init *) values into the box, // Do not propagate (* init *) values into the box,
// in fact, remove it from outside too // in fact, remove it from outside too
if (w->port_output) if (w->port_output)
w->attributes.erase(ID::init); w->attributes.erase(ID::init);
// Attach (* techmap_autopurge *) to all ports to ensure that
// undriven inputs/unused outputs are propagated through to
// the techmapped cell
w->attributes[ID::techmap_autopurge] = 1;
replace_cell->setPort(port, w);
} }
unmap_module->ports = derived_module->ports; unmap_module->ports = derived_module->ports;
unmap_module->check(); unmap_module->check();
auto replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
for (const auto &conn : cell->connections()) {
auto w = unmap_module->wire(conn.first);
log_assert(w);
replace_cell->setPort(conn.first, w);
}
replace_cell->parameters = cell->parameters; replace_cell->parameters = cell->parameters;
} }
} }