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cellmatch: Size the `lut` attribute

This commit is contained in:
Martin Povišer 2024-10-02 11:26:15 +02:00
parent 1bf908dea8
commit ec42b42bd9
1 changed files with 1 additions and 1 deletions
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2
passes/techmap/cellmatch.cc
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@ -223,7 +223,7 @@ struct CellmatchPass : Pass {
for (auto bit : outputs) { for (auto bit : outputs) {
log_assert(bit.is_wire()); log_assert(bit.is_wire());
bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]); bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
bit.wire->attributes[ID(lut)] = luts[no++]; bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
} }
} }