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Merge pull request #1870 from boqwxp/cleanup_setattr 

Clean up `passes/cmds/setattr.cc`.
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whitequark 2020-04-06 11:04:49 +00:00 committed by GitHub
parent df95dc7d4a 2e27ddd511
commit ebf23cd62e
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 14 additions and 22 deletions
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32
passes/cmds/setattr.cc
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@ -38,7 +38,7 @@ struct setunset_t
value = RTLIL::Const(set_value.substr(1, GetSize(set_value)-2)); value = RTLIL::Const(set_value.substr(1, GetSize(set_value)-2));
} else { } else {
RTLIL::SigSpec sig_value; RTLIL::SigSpec sig_value;
if (!RTLIL::SigSpec::parse(sig_value, NULL, set_value)) if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value))
log_cmd_error("Can't decode value '%s'!\n", set_value.c_str()); log_cmd_error("Can't decode value '%s'!\n", set_value.c_str());
value = sig_value.as_const(); value = sig_value.as_const();
} }
@ -96,10 +96,8 @@ struct SetattrPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto &mod : design->modules_) for (auto module : design->modules())
{ {
RTLIL::Module *module = mod.second;
if (flag_mod) { if (flag_mod) {
if (design->selected_whole_module(module->name)) if (design->selected_whole_module(module->name))
do_setunset(module->attributes, setunset_list); do_setunset(module->attributes, setunset_list);
@ -109,17 +107,17 @@ struct SetattrPass : public Pass {
if (!design->selected(module)) if (!design->selected(module))
continue; continue;
for (auto &it : module->wires_) for (auto wire : module->wires())
if (design->selected(module, it.second)) if (design->selected(module, wire))
do_setunset(it.second->attributes, setunset_list); do_setunset(wire->attributes, setunset_list);
for (auto &it : module->memories) for (auto &it : module->memories)
if (design->selected(module, it.second)) if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list); do_setunset(it.second->attributes, setunset_list);
for (auto &it : module->cells_) for (auto cell : module->cells())
if (design->selected(module, it.second)) if (design->selected(module, cell))
do_setunset(it.second->attributes, setunset_list); do_setunset(cell->attributes, setunset_list);
for (auto &it : module->processes) for (auto &it : module->processes)
if (design->selected(module, it.second)) if (design->selected(module, it.second))
@ -208,18 +206,12 @@ struct SetparamPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto &mod : design->modules_) for (auto module : design->selected_modules())
{ {
RTLIL::Module *module = mod.second; for (auto cell : module->selected_cells()) {
if (!design->selected(module))
continue;
for (auto &it : module->cells_)
if (design->selected(module, it.second)) {
if (!new_cell_type.empty()) if (!new_cell_type.empty())
it.second->type = new_cell_type; cell->type = new_cell_type;
do_setunset(it.second->parameters, setunset_list); do_setunset(cell->parameters, setunset_list);
} }
} }
} }