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quicklogic: allow fractured mode on canonical dspv1 modules

This commit is contained in:
Emil J. Tywoniak 2025-03-06 12:55:26 +01:00
parent 6685f92c93
commit ebbac1f421
2 changed files with 6 additions and 4 deletions
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5
techlibs/quicklogic/qlf_k6n10f/dspv1_final_map.v
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@ -34,7 +34,8 @@ module dsp_t1_20x18x64_cfg_ports (
input [5:0] shift_right_i, input [5:0] shift_right_i,
input round_i, input round_i,
input subtract_i, input subtract_i,
input register_inputs_i input register_inputs_i,
input f_mode_i
); );
parameter [19:0] COEFF_0 = 20'd0; parameter [19:0] COEFF_0 = 20'd0;
@ -59,7 +60,7 @@ module dsp_t1_20x18x64_cfg_ports (
.unsigned_a (unsigned_a_i), .unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i), .unsigned_b (unsigned_b_i),
.f_mode (1'b0), // No fracturation .f_mode (f_mode_i), // No fracturation
.output_select (output_select_i), .output_select (output_select_i),
.saturate_enable (saturate_enable_i), .saturate_enable (saturate_enable_i),
.shift_right (shift_right_i), .shift_right (shift_right_i),

5
techlibs/quicklogic/qlf_k6n10f/dspv1_sim.v
View File

@ -4195,7 +4195,8 @@ module dsp_t1_20x18x64_cfg_ports (
input wire [ 5:0] shift_right_i, input wire [ 5:0] shift_right_i,
input wire round_i, input wire round_i,
input wire subtract_i, input wire subtract_i,
input wire register_inputs_i input wire register_inputs_i,
input wire f_mode_i
); );
parameter [19:0] COEFF_0 = 20'd0; parameter [19:0] COEFF_0 = 20'd0;
@ -4211,7 +4212,7 @@ module dsp_t1_20x18x64_cfg_ports (
.z(z_o), .z(z_o),
.dly_b(dly_b_o), .dly_b(dly_b_o),
.f_mode(1'b0), // 20x18x64 DSP .f_mode(f_mode_i), // 20x18x64 DSP
.acc_fir(acc_fir_i), .acc_fir(acc_fir_i),
.feedback(feedback_i), .feedback(feedback_i),