mirror of https://github.com/YosysHQ/yosys.git
verilog: fix specify src attribute
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584780d776
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@ -885,6 +885,7 @@ specify_item:
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cell->str = stringf("$specify$%d", autoidx++);
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cell->children.push_back(new AstNode(AST_CELLTYPE));
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cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
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SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
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char oper_polarity = 0;
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char oper_type = oper->at(0);
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@ -973,6 +974,7 @@ specify_item:
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cell->str = stringf("$specify$%d", autoidx++);
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cell->children.push_back(new AstNode(AST_CELLTYPE));
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cell->children.back()->str = "$specrule";
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SET_AST_NODE_LOC(cell, @1, @14);
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cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
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cell->children.back()->str = "\\TYPE";
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@ -4,10 +4,16 @@ cd test
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select t:$specify2 -assert-count 0
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select t:$specify3 -assert-count 1
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select t:$specrule -assert-count 2
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select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1
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select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1
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select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1
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cd test2
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select t:$specify2 -assert-count 2
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select t:$specify3 -assert-count 0
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select t:$specrule -assert-count 0
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select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1
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# ^^ Note use of macro
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select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1
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cd
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write_verilog specify.out
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design -stash gold
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