mirror of https://github.com/YosysHQ/yosys.git
Add inout ports to cells_xtra.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -1,13 +1,13 @@
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#!/bin/bash
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set -e
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libdir="/opt/Xilinx/Vivado/2015.4/data/verilog/src"
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libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
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function xtract_cell_decl()
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{
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for dir in $libdir/xeclib $libdir/retarget; do
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[ -f $dir/$1.v ] || continue
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egrep '^\s*((end)?module|parameter|input|output|(end)?function|(end)?task)' $dir/$1.v |
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egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
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sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
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s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
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s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
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@ -2237,6 +2237,7 @@ module IOBUF_DCIEN (...);
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parameter SLEW = "SLOW";
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parameter USE_IBUFDISABLE = "TRUE";
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output O;
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inout IO;
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input DCITERMDISABLE;
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input I;
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input IBUFDISABLE;
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@ -2251,6 +2252,7 @@ module IOBUF_INTERMDISABLE (...);
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parameter SLEW = "SLOW";
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parameter USE_IBUFDISABLE = "TRUE";
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output O;
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inout IO;
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input I;
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input IBUFDISABLE;
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input INTERMDISABLE;
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@ -2264,6 +2266,7 @@ module IOBUFDS (...);
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parameter IOSTANDARD = "DEFAULT";
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parameter SLEW = "SLOW";
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output O;
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inout IO, IOB;
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input I, T;
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endmodule
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@ -2276,6 +2279,8 @@ module IOBUFDS_DCIEN (...);
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parameter SLEW = "SLOW";
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parameter USE_IBUFDISABLE = "TRUE";
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output O;
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inout IO;
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inout IOB;
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input DCITERMDISABLE;
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input I;
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input IBUFDISABLE;
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@ -2289,6 +2294,8 @@ module IOBUFDS_DIFF_OUT (...);
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parameter IOSTANDARD = "DEFAULT";
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output O;
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output OB;
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inout IO;
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inout IOB;
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input I;
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input TM;
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input TS;
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@ -2303,6 +2310,8 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
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parameter USE_IBUFDISABLE = "TRUE";
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output O;
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output OB;
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inout IO;
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inout IOB;
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input DCITERMDISABLE;
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input I;
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input IBUFDISABLE;
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@ -2319,6 +2328,8 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
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parameter USE_IBUFDISABLE = "TRUE";
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output O;
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output OB;
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inout IO;
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inout IOB;
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input I;
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input IBUFDISABLE;
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input INTERMDISABLE;
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@ -2382,6 +2393,7 @@ module ISERDESE2 (...);
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endmodule
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module KEEPER (...);
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inout O;
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endmodule
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module LDCE (...);
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