mirror of https://github.com/YosysHQ/yosys.git
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
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parent
9e072ec21f
commit
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@ -63,6 +63,9 @@ struct SynthIce40Pass : public ScriptPass
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log(" -relut\n");
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log(" combine LUTs after synthesis\n");
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log("\n");
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log(" -nocarry\n");
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log(" do not use SB_CARRY cells in output netlist\n");
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log("\n");
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@ -90,7 +93,7 @@ struct SynthIce40Pass : public ScriptPass
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}
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string top_opt, blif_file, edif_file, json_file;
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bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
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bool nocarry, nodffe, nobram, flatten, retime, relut, abc2, vpr;
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int min_ce_use;
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void clear_flags() YS_OVERRIDE
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@ -105,6 +108,7 @@ struct SynthIce40Pass : public ScriptPass
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nobram = false;
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flatten = true;
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retime = false;
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relut = false;
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abc2 = false;
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vpr = false;
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}
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@ -153,6 +157,10 @@ struct SynthIce40Pass : public ScriptPass
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retime = true;
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continue;
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}
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if (args[argidx] == "-relut") {
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relut = true;
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continue;
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}
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if (args[argidx] == "-nocarry") {
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nocarry = true;
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continue;
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@ -259,6 +267,10 @@ struct SynthIce40Pass : public ScriptPass
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run("techmap -map +/ice40/latches_map.v");
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run("abc -lut 4");
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run("clean");
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if (relut || help_mode) {
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run("ice40_unlut", "(only if -relut)");
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run("opt_lut", " (only if -relut)");
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}
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}
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if (check_label("map_cells"))
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