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No point logging constant bit

This commit is contained in:
Eddie Hung 2019-06-21 12:46:55 -07:00
parent 950bb4c242
commit ea154d5ff4
1 changed files with 1 additions and 1 deletions
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2
backends/aiger/xaiger.cc
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@ -110,7 +110,7 @@ struct XAigerWriter
}
if (bit == State::Sx || bit == State::Sz) {
log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit));
log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
a = aig_map.at(State::S0);
}