riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

No point logging constant bit

This commit is contained in:
Eddie Hung 2019-06-21 12:46:55 -07:00
parent 950bb4c242
commit ea154d5ff4
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/aiger/xaiger.cc
View File

@ -110,7 +110,7 @@ struct XAigerWriter
} }
if (bit == State::Sx || bit == State::Sz) { if (bit == State::Sx || bit == State::Sz) {
log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit)); log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
a = aig_map.at(State::S0); a = aig_map.at(State::S0);
} }