mirror of https://github.com/YosysHQ/yosys.git
backends/verilog: Support meminit with mask.
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19720b970d
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@ -504,9 +504,24 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
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int start = init.addr.as_int();
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int start = init.addr.as_int();
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for (int i=0; i<words; i++)
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for (int i=0; i<words; i++)
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{
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{
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f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i + start);
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for (int j = 0; j < mem.width; j++)
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dump_const(f, init.data.extract(i*mem.width, mem.width));
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{
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f << stringf(";\n");
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if (init.en[j] != State::S1)
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continue;
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int start_j = j, width = 1;
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while (j+1 < mem.width && init.en[j+1] == State::S1)
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j++, width++;
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if (width == mem.width) {
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f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i + start);
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} else {
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f << stringf("%s" " %s[%d][%d:%d] = ", indent.c_str(), mem_id.c_str(), i + start, j, start_j);
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}
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dump_const(f, init.data.extract(i*mem.width+start_j, width));
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f << stringf(";\n");
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}
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}
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}
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}
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}
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f << stringf("%s" "end\n", indent.c_str());
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f << stringf("%s" "end\n", indent.c_str());
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