Indenting fixes in gowin sim cell lib

techlibs/gowin/cells_sim.v

@@ -25,12 +25,16 @@ module LUT4(output F, input I0, I1, I2, I3);
 endmodule
 
 module DFF (output reg Q, input CLK, D);
-	always @(posedge C)
+	parameter [0:0] INIT = 1'b0;
+	initial Q = INIT;
+	always @(posedge CLK)
 		Q <= D;
 endmodule
 
 module DFFN (output reg Q, input CLK, D);
-	always @(negedge C)
+	parameter [0:0] INIT = 1'b0;
+	initial Q = INIT;
+	always @(negedge CLK)
 		Q <= D;
 endmodule
 
@@ -49,3 +53,7 @@ endmodule
 module OBUF(output O, input I);
 	assign O = I;
 endmodule
+
+module GSR (input GSRI);
+	wire GSRO = GSRI;
+endmodule