riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

duplicate -> clone

This commit is contained in:
Eddie Hung 2019-07-12 19:33:02 -07:00
parent be0cb7f4b8
commit e9bdc86c0e
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/techmap/abc9.cc
View File

@ -761,11 +761,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
auto jt = bit2sinks.find(a_bit); auto jt = bit2sinks.find(a_bit);
if (jt == bit2sinks.end()) if (jt == bit2sinks.end())
goto duplicate_lut; goto clone_lut;
for (auto sink_cell : jt->second) for (auto sink_cell : jt->second)
if (sink_cell->type != "$lut") if (sink_cell->type != "$lut")
goto duplicate_lut; goto clone_lut;
// Push downstream LUTs past inverter // Push downstream LUTs past inverter
for (auto sink_cell : jt->second) { for (auto sink_cell : jt->second) {
@ -787,7 +787,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
sink_cell->setParam("\\LUT", mask); sink_cell->setParam("\\LUT", mask);
} }
duplicate_lut: clone_lut:
driver_mask = driver_lut->getParam("\\LUT"); driver_mask = driver_lut->getParam("\\LUT");
for (auto &b : driver_mask.bits) { for (auto &b : driver_mask.bits) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1; if (b == RTLIL::State::S0) b = RTLIL::State::S1;