riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' of github.com:YosysHQ/yosys

This commit is contained in:
Clifford Wolf 2019-03-07 22:44:50 -08:00
parent a330c68363 df0598f455
commit e9b34ad5c0
6 changed files with 12 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
examples/anlogic/.gitignore vendored
View File

@ -1,4 +1,7 @@
demo.bit demo.bit
demo_phy.area demo_phy.area
full.v full.v
*.log *.log
*.h
*.tde
*.svf

1
examples/anlogic/README
View File

@ -10,4 +10,3 @@ set TD_HOME env variable to the full path to the TD <TD Install Directory> as fo
export TD_HOME=<TD Install Directory> export TD_HOME=<TD Install Directory>
then run "bash build.sh" in this directory. then run "bash build.sh" in this directory.

2
examples/anlogic/build.tcl
View File

@ -8,4 +8,4 @@ pack
place place
route route
report_area -io_info -file demo_phy.area report_area -io_info -file demo_phy.area
bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000 bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000

2
examples/anlogic/demo.adc
View File

@ -1,2 +1,2 @@
set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ
set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED

10
examples/anlogic/demo.v
View File

@ -1,18 +1,18 @@
module demo ( module demo (
input wire CLK_IN, input wire CLK_IN,
output wire R_LED output wire R_LED
); );
parameter time1 = 30'd12_000_000; parameter time1 = 30'd12_000_000;
reg led_state; reg led_state;
reg [29:0] count; reg [29:0] count;
always @(posedge CLK_IN)begin always @(posedge CLK_IN)begin
if(count == time1)begin if(count == time1)begin
count<= 30'd0; count<= 30'd0;
led_state <= ~led_state; led_state <= ~led_state;
end end
else else
count <= count + 1'b1; count <= count + 1'b1;
end end
assign R_LED = led_state; assign R_LED = led_state;
endmodule endmodule

2
examples/anlogic/demo.ys
View File

@ -1,3 +1,3 @@
read_verilog demo.v read_verilog demo.v
synth_anlogic -top demo synth_anlogic -top demo
write_verilog full.v write_verilog full.v