mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: don't emit syncs for empty lhs.
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@ -1138,7 +1138,7 @@ struct CxxrtlWorker {
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f << indent << "// cell " << cell->name.str() << " syncs\n";
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for (auto conn : cell->connections())
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if (cell->output(conn.first))
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if (is_cxxrtl_sync_port(cell, conn.first)) {
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if (is_cxxrtl_sync_port(cell, conn.first) && !conn.second.empty()) {
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f << indent;
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dump_sigspec_lhs(conn.second, for_debug);
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f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
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