mirror of https://github.com/YosysHQ/yosys.git
Fix broken CI, check reset even for constants, trim rstmux
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parent
e4bd5aaebf
commit
e9645c7fa7
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@ -74,9 +74,9 @@ code
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return lhs == rhs;
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return lhs == rhs;
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};
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};
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int i = width;
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int i = width-1;
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while (i > 2) {
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while (i > 1) {
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i--;
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log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]);
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if (D[i] != D[i-1])
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if (D[i] != D[i-1])
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break;
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break;
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if (!cmpx(rst[i], rst[i-1]))
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if (!cmpx(rst[i], rst[i-1]))
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@ -86,26 +86,36 @@ code
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if (!cmpx(rst[i], init[i]))
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if (!cmpx(rst[i], init[i]))
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break;
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break;
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module->connect(Q[i], Q[i-1]);
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module->connect(Q[i], Q[i-1]);
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did_something = true;
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i--;
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}
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}
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if (i < width-1) {
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if (i < width-1) {
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did_something = true;
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if (cemux) {
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if (cemux) {
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SigSpec &ceA = cemux->connections_.at(\A);
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SigSpec &ceA = cemux->connections_.at(\A);
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SigSpec &ceB = cemux->connections_.at(\B);
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SigSpec &ceB = cemux->connections_.at(\B);
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SigSpec &ceY = cemux->connections_.at(\Y);
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SigSpec &ceY = cemux->connections_.at(\Y);
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ceA.remove(i, width-i);
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ceA.remove(i, width-1-i);
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ceB.remove(i, width-i);
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ceB.remove(i, width-1-i);
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ceY.remove(i, width-i);
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ceY.remove(i, width-1-i);
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cemux->fixup_parameters();
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cemux->fixup_parameters();
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}
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}
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dffD.remove(i, width-i);
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if (rstmux) {
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dffQ.remove(i, width-i);
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SigSpec &rstA = rstmux->connections_.at(\A);
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SigSpec &rstB = rstmux->connections_.at(\B);
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SigSpec &rstY = rstmux->connections_.at(\Y);
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rstA.remove(i, width-1-i);
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rstB.remove(i, width-1-i);
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rstY.remove(i, width-1-i);
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rstmux->fixup_parameters();
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}
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dffD.remove(i, width-1-i);
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dffQ.remove(i, width-1-i);
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dff->fixup_parameters();
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dff->fixup_parameters();
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log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
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log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux, "n/a"), log_id(rstmux, "n/a"), width-1-i);
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accept;
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width = i+1;
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}
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}
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else if (cemux) {
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if (cemux) {
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SigSpec &ceA = cemux->connections_.at(\A);
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SigSpec &ceA = cemux->connections_.at(\A);
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SigSpec &ceB = cemux->connections_.at(\B);
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SigSpec &ceB = cemux->connections_.at(\B);
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SigSpec &ceY = cemux->connections_.at(\Y);
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SigSpec &ceY = cemux->connections_.at(\Y);
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@ -114,15 +124,7 @@ code
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for (int i = width-1; i >= 0; i--) {
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for (int i = width-1; i >= 0; i--) {
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if (D[i].wire)
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if (D[i].wire)
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continue;
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continue;
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Wire *w = Q[i].wire;
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if (cmpx(rst[i], D[i].data) && cmpx(init[i], D[i].data)) {
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auto it = w->attributes.find(\init);
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State init;
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if (it != w->attributes.end())
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init = it->second[Q[i].offset];
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else
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init = State::Sx;
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if (init == State::Sx || init == D[i].data) {
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count++;
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count++;
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module->connect(Q[i], D[i]);
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module->connect(Q[i], D[i]);
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ceA.remove(i);
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ceA.remove(i);
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@ -136,9 +138,10 @@ code
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did_something = true;
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did_something = true;
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cemux->fixup_parameters();
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cemux->fixup_parameters();
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dff->fixup_parameters();
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dff->fixup_parameters();
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log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
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log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), log_id(rstmux, "n/a"), count);
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}
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}
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accept;
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}
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}
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if (did_something)
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accept;
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endcode
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endcode
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@ -131,8 +131,8 @@ EOT
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proc
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proc
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equiv_opt -assert peepopt
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equiv_opt -assert peepopt
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design -load postopt
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=5 %i
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select -assert-count 1 t:$dff r:WIDTH=4 %i
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select -assert-count 1 t:$mux r:WIDTH=5 %i
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select -assert-count 1 t:$mux r:WIDTH=4 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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####################
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####################
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