mirror of https://github.com/YosysHQ/yosys.git
$size() now works correctly for all cases!
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
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6ddc6a7af4
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@ -1883,6 +1883,8 @@ skip_dynamic_range_lvalue_expansion:;
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int dim = 1;
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int dim = 1;
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if (str == "\\$size" && children.size() == 2) {
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if (str == "\\$size" && children.size() == 2) {
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AstNode *buf = children[1]->clone();
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AstNode *buf = children[1]->clone();
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// Evaluate constant expression
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while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
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dim = buf->asInt(false);
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dim = buf->asInt(false);
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delete buf;
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delete buf;
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}
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}
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@ -1890,10 +1892,10 @@ skip_dynamic_range_lvalue_expansion:;
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int mem_depth = 1;
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int mem_depth = 1;
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AstNode *id_ast = NULL;
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AstNode *id_ast = NULL;
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// Is this needed?
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// Is this needed?
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//while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
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//while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
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buf->detectSignWidth(width_hint, sign_hint);
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buf->detectSignWidth(width_hint, sign_hint);
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if (buf->type == AST_IDENTIFIER) {
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if (buf->type == AST_IDENTIFIER) {
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id_ast = buf->id2ast;
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id_ast = buf->id2ast;
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if (id_ast == NULL && current_scope.count(buf->str))
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if (id_ast == NULL && current_scope.count(buf->str))
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@ -1907,30 +1909,28 @@ skip_dynamic_range_lvalue_expansion:;
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if (str == "\\$bits") {
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if (str == "\\$bits") {
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if (mem_range->type == AST_RANGE) {
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if (mem_range->type == AST_RANGE) {
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if (!mem_range->range_valid)
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if (!mem_range->range_valid)
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log_error("Failed to detect width of memory access `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
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log_error("Failed to detect width of memory access `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
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mem_depth = mem_range->range_left - mem_range->range_right + 1;
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mem_depth = mem_range->range_left - mem_range->range_right + 1;
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} else if (mem_range->type == AST_MULTIRANGE) {
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for (auto n : mem_range->children)
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mem_depth *= (n->range_left - n->range_right + 1);
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} else
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} else
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log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
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log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
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} else {
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} else {
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// $size()
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// $size()
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if (mem_range->type == AST_RANGE) {
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if (mem_range->type == AST_RANGE) {
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if (!mem_range->range_valid)
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if (!mem_range->range_valid)
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log_error("Failed to detect width of memory access `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
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log_error("Failed to detect width of memory access `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
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int dims;
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if (id_ast->multirange_dimensions.empty())
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dims = 1;
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else
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dims = GetSize(id_ast->multirange_dimensions)/2;
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if (dim == 1)
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if (dim == 1)
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width_hint = mem_range->range_left - mem_range->range_right + 1;
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width_hint = (dims > 1) ? id_ast->multirange_dimensions[1] : (mem_range->range_left - mem_range->range_right + 1);
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} else if (mem_range->type == AST_MULTIRANGE) {
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else if (dim <= dims) {
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log("multirange!\n");
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width_hint = id_ast->multirange_dimensions[2*dim-1];
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int s = mem_range->children.size();
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} else if ((dim > dims+1) || (dim < 0))
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if (dim <= s) {
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log_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d at %s:%d!\n", dim, buf->str.c_str(), dims+1, filename.c_str(), linenum);
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auto n = mem_range->children[dim-1];
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width_hint = (n->range_left - n->range_right + 1);
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} else if (dim > s+1)
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log_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d at %s:%d!\n", dim, mem_range->str.c_str(), s+1, filename.c_str(), linenum);
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} else
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} else
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log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", mem_range->str.c_str(), filename.c_str(), linenum);
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log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
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}
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}
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}
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}
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}
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}
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@ -1,8 +1,8 @@
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module functions01;
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module functions01;
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wire [3:0]x;
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wire [5:2]x;
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wire [3:0]y[0:5];
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wire [3:0]y[2:7];
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wire [3:0]z[0:5][0:7];
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wire [3:0]z[7:2][2:9];
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//wire [$size(x)-1:0]x_size;
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//wire [$size(x)-1:0]x_size;
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//wire [$size({x, x})-1:0]xx_size;
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//wire [$size({x, x})-1:0]xx_size;
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@ -13,7 +13,14 @@ assert property ($size(x) == 4);
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assert property ($size({3{x}}) == 3*4);
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assert property ($size({3{x}}) == 3*4);
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assert property ($size(y) == 6);
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assert property ($size(y) == 6);
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assert property ($size(y, 1) == 6);
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assert property ($size(y, 1) == 6);
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assert property ($size(y, 2) == 4);
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assert property ($size(y, (1+1)) == 4);
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assert property ($size(z) == 6);
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assert property ($size(z, 1) == 6);
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assert property ($size(z, 2) == 8);
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assert property ($size(z, 3) == 4);
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// This should trigger an error if enabled (it does).
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//assert property ($size(z, 4) == 4);
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//wire [$bits(x)-1:0]x_bits;
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//wire [$bits(x)-1:0]x_bits;
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//wire [$bits({x, x})-1:0]xx_bits;
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//wire [$bits({x, x})-1:0]xx_bits;
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@ -22,5 +29,4 @@ assert property ($bits(x) == 4);
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assert property ($bits(y) == 4*6);
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assert property ($bits(y) == 4*6);
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assert property ($bits(z) == 4*6*8);
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assert property ($bits(z) == 4*6*8);
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endmodule
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endmodule
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