From e8e806f2ca289749cc5a7c7ddba11c55965bb54b Mon Sep 17 00:00:00 2001
From: Alain Dargelas <alain@silimate.com>
Date: Thu, 19 Dec 2024 13:54:25 -0800
Subject: [PATCH] Consolidate tests

---
 tests/peepopt/muldiv_c.ys  | 42 ++++++++++++++++++++++++++++++++++++++
 tests/peepopt/multdiv_c.ys | 39 -----------------------------------
 2 files changed, 42 insertions(+), 39 deletions(-)
 delete mode 100644 tests/peepopt/multdiv_c.ys

diff --git a/tests/peepopt/muldiv_c.ys b/tests/peepopt/muldiv_c.ys
index 2d57e5b6b..892f0b533 100644
--- a/tests/peepopt/muldiv_c.ys
+++ b/tests/peepopt/muldiv_c.ys
@@ -1,3 +1,45 @@
+log -header "Test simple positive case"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire  [11:0] a,
+  output wire  [11:0] y
+);
+  assign y = (a * 16'd5140) / (257 * 2);
+endmodule
+EOF
+check -assert
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-none t:$div
+design -reset
+
+
+log -pop
+log -header "Test negative case where div is kept"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire signed [11:0] a,
+  output wire signed [31:0] y,
+  output wire probe
+);
+   wire [28:0] tmp = (a * 16'd5140);
+   assign probe = tmp[28];
+
+  assign y = tmp[27:0] / (257 * 2);
+endmodule
+EOF
+check -assert
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-any t:$div
+design -reset
+
+
+
 # Basic pattern transformed: (a * b) / c
 read_verilog <<EOT
 module top(
diff --git a/tests/peepopt/multdiv_c.ys b/tests/peepopt/multdiv_c.ys
deleted file mode 100644
index fa8f0d38d..000000000
--- a/tests/peepopt/multdiv_c.ys
+++ /dev/null
@@ -1,39 +0,0 @@
-log -header "Test simple positive case"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire  [11:0] a,
-  output wire  [11:0] y
-);
-  assign y = (a * 16'd5140) / (257 * 2);
-endmodule
-EOF
-check -assert
-equiv_opt -assert peepopt
-design -load postopt
-select -assert-none t:$div
-design -reset
-
-
-log -pop
-log -header "Test negative case where div is kept"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire signed [11:0] a,
-  output wire signed [31:0] y,
-  output wire probe
-);
-   wire [28:0] tmp = (a * 16'd5140);
-   assign probe = tmp[28];
-
-  assign y = tmp[27:0] / (257 * 2);
-endmodule
-EOF
-check -assert
-equiv_opt -assert peepopt
-design -load postopt
-select -assert-any t:$div
-design -reset