mirror of https://github.com/YosysHQ/yosys.git
Add -hidden option to submod
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da51492dbc
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@ -37,6 +37,7 @@ struct SubmodWorker
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pool<SigBit> outputs;
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bool copy_mode;
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bool hidden_mode;
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std::string opt_name;
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struct SubModule
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@ -149,19 +150,29 @@ struct SubmodWorker
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else
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new_wire_name = stringf("%s[%d]", wire->name.c_str(), bit.offset);
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if (new_wire_port_input || new_wire_port_output) {
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while (new_wire_name[0] == '$') {
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std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
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if (new_wire_name[0] == '$')
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do {
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std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : ":", auto_name_counter++);
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if (all_wire_names.count(next_wire_name) == 0) {
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all_wire_names.insert(next_wire_name);
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new_wire_name = next_wire_name;
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}
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}
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} while (new_wire_name[0] == '$');
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else
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new_wire_name = stringf("$submod%s\n", new_wire_name.c_str());
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}
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RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name);
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new_wire->port_input = new_wire_port_input;
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new_wire->port_output = new_wire_port_output;
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new_wire->attributes = wire->attributes;
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if (new_wire->port_output) {
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auto it = wire->attributes.find(ID(init));
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if (it != wire->attributes.end()) {
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new_wire->attributes[ID(init)] = it->second[bit.offset];
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it->second[bit.offset] = State::Sx;
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}
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}
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if (new_wire->port_input && new_wire->port_output)
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log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
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@ -204,8 +215,8 @@ struct SubmodWorker
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}
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}
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SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, std::string opt_name = std::string()) :
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design(design), module(module), sigmap(module), copy_mode(copy_mode), opt_name(opt_name)
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SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, bool hidden_mode = false, std::string opt_name = std::string()) :
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design(design), module(module), sigmap(module), copy_mode(copy_mode), hidden_mode(hidden_mode), opt_name(opt_name)
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{
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if (!design->selected_whole_module(module->name) && opt_name.empty())
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return;
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@ -289,7 +300,7 @@ struct SubmodPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" submod [-copy] [selection]\n");
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log(" submod [options] [selection]\n");
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log("\n");
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log("This pass identifies all cells with the 'submod' attribute and moves them to\n");
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log("a newly created module. The value of the attribute is used as name for the\n");
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@ -301,16 +312,20 @@ struct SubmodPass : public Pass {
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log("This pass only operates on completely selected modules with no processes\n");
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log("or memories.\n");
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log("\n");
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log(" -copy\n");
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log(" by default the cells are 'moved' from the source module and the source\n");
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log(" module will use an instance of the new module after this command is\n");
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log(" finished. call with -copy to not modify the source module.\n");
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log("\n");
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log(" submod -name <name> [-copy] [selection]\n");
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log(" -name <name>\n");
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log(" don't use the 'submod' attribute but instead use the selection. only\n");
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log(" objects from one module might be selected. the value of the -name option\n");
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log(" is used as the value of the 'submod' attribute instead.\n");
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log("\n");
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log("As above, but don't use the 'submod' attribute but instead use the selection.\n");
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log("Only objects from one module might be selected. The value of the -name option\n");
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log("is used as the value of the 'submod' attribute above.\n");
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log("\n");
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log("By default the cells are 'moved' from the source module and the source module\n");
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log("will use an instance of the new module after this command is finished. Call\n");
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log("with -copy to not modify the source module.\n");
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log(" -hidden\n");
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log(" instead of creating submodule ports with public names, create ports with\n");
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log(" private names so that a subsequent 'flatten; clean' call will restore the\n");
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log(" original module with original public names.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -320,6 +335,7 @@ struct SubmodPass : public Pass {
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std::string opt_name;
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bool copy_mode = false;
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bool hidden_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -331,6 +347,10 @@ struct SubmodPass : public Pass {
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copy_mode = true;
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continue;
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}
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if (args[argidx] == "-hidden") {
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hidden_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -351,7 +371,7 @@ struct SubmodPass : public Pass {
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queued_modules.push_back(mod_it.first);
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for (auto &modname : queued_modules)
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if (design->modules_.count(modname) != 0) {
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SubmodWorker worker(design, design->modules_[modname], copy_mode);
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SubmodWorker worker(design, design->modules_[modname], copy_mode, hidden_mode);
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handled_modules.insert(modname);
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did_something = true;
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}
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@ -374,7 +394,7 @@ struct SubmodPass : public Pass {
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else {
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Pass::call_on_module(design, module, "opt_clean");
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log_header(design, "Continuing SUBMOD pass.\n");
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SubmodWorker worker(design, module, copy_mode, opt_name);
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SubmodWorker worker(design, module, copy_mode, hidden_mode, opt_name);
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}
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}
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