From e89cc9c02fc5d9ff2a6eedc524e7c0420666ac22 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 4 Aug 2020 16:30:24 +0200
Subject: [PATCH] peepopt.muldiv: Add a signedness check.

Fixes #2318.
---
 passes/pmgen/peepopt_muldiv.pmg |  5 ++++-
 tests/opt/bug2318.ys            | 12 ++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 tests/opt/bug2318.ys

diff --git a/passes/pmgen/peepopt_muldiv.pmg b/passes/pmgen/peepopt_muldiv.pmg
index 7cad759d0..a4e232342 100644
--- a/passes/pmgen/peepopt_muldiv.pmg
+++ b/passes/pmgen/peepopt_muldiv.pmg
@@ -1,16 +1,18 @@
 pattern muldiv
 
 state <SigSpec> t x y
+state <bool> is_signed
 
 match mul
 	select mul->type == $mul
 	select GetSize(port(mul, \A)) + GetSize(port(mul, \B)) <= GetSize(port(mul, \Y))
 endmatch
 
-code t x y
+code t x y is_signed
 	t = port(mul, \Y);
 	x = port(mul, \A);
 	y = port(mul, \B);
+	is_signed = param(mul, \A_SIGNED).as_bool();
 	branch;
 	std::swap(x, y);
 endcode
@@ -19,6 +21,7 @@ match div
 	select div->type.in($div)
 	index <SigSpec> port(div, \A) === t
 	index <SigSpec> port(div, \B) === x
+	filter param(div, \A_SIGNED).as_bool() == is_signed
 endmatch
 
 code
diff --git a/tests/opt/bug2318.ys b/tests/opt/bug2318.ys
new file mode 100644
index 000000000..9de6f88ec
--- /dev/null
+++ b/tests/opt/bug2318.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module t(input [3:0] A, input [3:0] B, output signed [3:0] Y);
+
+wire [7:0] P = A * B;
+wire signed [7:0] SP = P;
+wire signed [3:0] SB = B;
+assign Y = SP / SB;
+
+endmodule
+EOT
+
+equiv_opt -assert peepopt