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Cleanup

This commit is contained in:
Eddie Hung 2019-08-09 15:47:40 -07:00
parent 0b5b56c1ec
commit e83f231927
2 changed files with 18 additions and 18 deletions
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16
passes/pmgen/ice40_dsp.pmg
View File

@ -21,8 +21,8 @@ code sigH
endcode endcode
match ffA match ffA
if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
select ffA->type.in($dff) select ffA->type.in($dff)
filter mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
filter !port(mul, \A).remove_const().empty() filter !port(mul, \A).remove_const().empty()
filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set()) filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
optional optional
@ -44,8 +44,8 @@ code sigA clock clock_pol
endcode endcode
match ffB match ffB
if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
select ffB->type.in($dff) select ffB->type.in($dff)
filter mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
filter !port(mul, \B).remove_const().empty() filter !port(mul, \B).remove_const().empty()
filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set()) filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
optional optional
@ -73,11 +73,11 @@ code sigB clock clock_pol
endcode endcode
match ffH match ffH
if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
select ffH->type.in($dff) select ffH->type.in($dff)
select nusers(port(ffH, \D)) == 2 select nusers(port(ffH, \D)) == 2
index <SigSpec> port(ffH, \D) === sigH index <SigSpec> port(ffH, \D) === sigH
// Ensure pipeline register is not already used // Ensure pipeline register is not already used
filter mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
optional optional
endmatch endmatch
@ -154,7 +154,7 @@ endcode
match muxA match muxA
select muxA->type.in($mux) select muxA->type.in($mux)
select nusers(port(muxA, \A)) == 2 index <int> nusers(port(muxA, \A)) === 2
index <SigSpec> port(muxA, \A) === sigO index <SigSpec> port(muxA, \A) === sigO
optional optional
endmatch endmatch
@ -162,7 +162,7 @@ endmatch
match muxB match muxB
if !muxA if !muxA
select muxB->type.in($mux) select muxB->type.in($mux)
select nusers(port(muxB, \B)) == 2 index <int> nusers(port(muxB, \B)) === 2
index <SigSpec> port(muxB, \B) === sigO index <SigSpec> port(muxB, \B) === sigO
optional optional
endmatch endmatch
@ -185,16 +185,16 @@ code sigOused
endcode endcode
match ffO_lo match ffO_lo
if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
select ffO_lo->type.in($dff) select ffO_lo->type.in($dff)
filter nusers(sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()))) == 2
filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set()) filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set())
optional optional
endmatch endmatch
match ffO_hi match ffO_hi
if GetSize(sigOused) > 16
if nusers(sigOused.extract_end(16)) == 2
select ffO_hi->type.in($dff) select ffO_hi->type.in($dff)
filter GetSize(sigOused) > 16
filter nusers(sigOused.extract_end(16)) == 2
filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set()) filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set())
optional optional
endmatch endmatch

20
passes/pmgen/xilinx_dsp.pmg
View File

@ -9,11 +9,11 @@ match dsp
endmatch endmatch
match ffA match ffA
if param(dsp, \AREG).as_int() == 0
if !port(dsp, \A).remove_const().empty()
select ffA->type.in($dff) select ffA->type.in($dff)
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
select param(ffA, \CLK_POLARITY).as_bool() select param(ffA, \CLK_POLARITY).as_bool()
filter param(dsp, \AREG).as_int() == 0
filter !port(dsp, \A).remove_const().empty()
filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set()) filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
optional optional
endmatch endmatch
@ -24,11 +24,11 @@ code clock
endcode endcode
match ffB match ffB
if param(dsp, \BREG).as_int() == 0
if !port(dsp, \B).remove_const().empty()
select ffB->type.in($dff) select ffB->type.in($dff)
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
select param(ffB, \CLK_POLARITY).as_bool() select param(ffB, \CLK_POLARITY).as_bool()
filter param(dsp, \BREG).as_int() == 0
filter !port(dsp, \B).remove_const().empty()
filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set()) filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
optional optional
endmatch endmatch
@ -51,9 +51,9 @@ endcode
match addA match addA
select addA->type.in($add) select addA->type.in($add)
select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool() select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool()
select nusers(port(addA, \A)) == 2 index <int> nusers(port(addA, \A)) === 2
//index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int()) //index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int())
filter GetSize(sigP) >= param(addA, \A_WIDTH).as_int() filter param(addA, \A_WIDTH).as_int() <= GetSize(sigP)
filter port(addA, \A) == sigP.extract(0, param(addA, \A_WIDTH).as_int()) filter port(addA, \A) == sigP.extract(0, param(addA, \A_WIDTH).as_int())
optional optional
endmatch endmatch
@ -62,9 +62,9 @@ match addB
if !addA if !addA
select addB->type.in($add, $sub) select addB->type.in($add, $sub)
select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool() select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool()
select nusers(port(addB, \B)) == 2 index <int> nusers(port(addB, \B)) === 2
//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int()) //index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int())
filter GetSize(sigP) >= param(addB, \B_WIDTH).as_int() filter param(addB, \B_WIDTH).as_int() <= GetSize(sigP)
filter port(addB, \B) == sigP.extract(0, param(addB, \B_WIDTH).as_int()) filter port(addB, \B) == sigP.extract(0, param(addB, \B_WIDTH).as_int())
optional optional
endmatch endmatch
@ -110,12 +110,12 @@ code sigPused
endcode endcode
match ffP match ffP
if param(dsp, \PREG).as_int() == 0
if !sigPused.empty() if !sigPused.empty()
select ffP->type.in($dff) select ffP->type.in($dff)
select nusers(port(ffP, \D)) == 2 index <int> nusers(port(ffP, \D)) === 2
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
select param(ffP, \CLK_POLARITY).as_bool() select param(ffP, \CLK_POLARITY).as_bool()
filter param(dsp, \PREG).as_int() == 0
filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused) filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set()) filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
optional optional