From 67b4ce06e07fde80d5ac11cad4d673c501bdd421 Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Mon, 22 Jul 2019 12:15:22 +0100 Subject: [PATCH 01/12] intel: Map M9K BRAM only on families that have it This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM. --- techlibs/intel/Makefile.inc | 4 ++-- techlibs/intel/common/{brams.txt => brams_m9k.txt} | 0 .../intel/common/{brams_map.v => brams_map_m9k.v} | 0 techlibs/intel/synth_intel.cc | 13 ++++++++++--- 4 files changed, 12 insertions(+), 5 deletions(-) rename techlibs/intel/common/{brams.txt => brams_m9k.txt} (100%) rename techlibs/intel/common/{brams_map.v => brams_map_m9k.v} (100%) diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index ec7cea379..7a3d2c71a 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -3,8 +3,8 @@ OBJS += techlibs/intel/synth_intel.o $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v)) -$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt)) -$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v)) $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v)) $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v)) diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams_m9k.txt similarity index 100% rename from techlibs/intel/common/brams.txt rename to techlibs/intel/common/brams_m9k.txt diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map_m9k.v similarity index 100% rename from techlibs/intel/common/brams_map.v rename to techlibs/intel/common/brams_map_m9k.v diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index d7b089503..87d83f0db 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -187,8 +187,15 @@ struct SynthIntelPass : public ScriptPass { } if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/intel/common/brams.txt"); - run("techmap -map +/intel/common/brams_map.v"); + if (family_opt == "cycloneiv" || + family_opt == "cycloneive" || + family_opt == "max10" || + help_mode) { + run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)"); + run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)"); + } else { + log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str()); + } } if (check_label("map_ffram")) { @@ -217,7 +224,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { if (!noiopads) run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); - run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); + run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge"); From 49528ed3bd391c1ba3d50f2a904b6ffdb9d11250 Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Wed, 24 Jul 2019 10:38:15 +0100 Subject: [PATCH 02/12] intel: Make -noiopads the default --- techlibs/intel/synth_intel.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index d7b089503..539ba379f 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -61,8 +61,8 @@ struct SynthIntelPass : public ScriptPass { log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); - log(" -noiopads\n"); - log(" do not use IO pad cells in output netlist\n"); + log(" -iopads\n"); + log(" use IO pad cells in output netlist\n"); log("\n"); log(" -nobram\n"); log(" do not use block RAM cells in output netlist\n"); @@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass { } string top_opt, family_opt, vout_file, blif_file; - bool retime, flatten, nobram, noiopads; + bool retime, flatten, nobram, iopads; void clear_flags() YS_OVERRIDE { @@ -90,7 +90,7 @@ struct SynthIntelPass : public ScriptPass { retime = false; flatten = true; nobram = false; - noiopads = false; + iopads = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -125,8 +125,8 @@ struct SynthIntelPass : public ScriptPass { run_to = args[argidx].substr(pos + 1); continue; } - if (args[argidx] == "-noiopads") { - noiopads = true; + if (args[argidx] == "-iopads") { + iopads = true; continue; } if (args[argidx] == "-nobram") { @@ -215,8 +215,8 @@ struct SynthIntelPass : public ScriptPass { } if (check_label("map_cells")) { - if (!noiopads) - run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); + if (iopads || help_mode) + run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)"); run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); run("dffinit -highlow -ff dffeas q power_up"); From 25685a9a5b20c7c03b02d67f0a029702f0019e9d Mon Sep 17 00:00:00 2001 From: Jakob Wenzel Date: Wed, 24 Jul 2019 13:33:07 +0200 Subject: [PATCH 03/12] made ObjectIterator extend std::iterator this makes it possible to use std algorithms on them --- kernel/rtlil.h | 20 ++++++++++++++++++-- kernel/yosys.h | 1 + 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 82cbfaf28..10225cff2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -420,7 +420,11 @@ namespace RTLIL // It maintains a reference counter that is used to make sure that the container is not modified while being iterated over. template - struct ObjIterator + struct ObjIterator : public std::iterator { typename dict::iterator it; dict *list_p; @@ -474,13 +478,25 @@ namespace RTLIL return it != other.it; } - inline void operator++() { + + inline bool operator==(const RTLIL::ObjIterator &other) const { + return !(*this != other); + } + + inline ObjIterator& operator++() { log_assert(list_p != nullptr); if (++it == list_p->end()) { (*refcount_p)--; list_p = nullptr; refcount_p = nullptr; } + return *this; + } + + inline const ObjIterator operator++(int) { + ObjIterator result(*this); + ++(*this); + return result; } }; diff --git a/kernel/yosys.h b/kernel/yosys.h index c7b671724..84c797b2d 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -52,6 +52,7 @@ #include #include #include +#include #include #include From 173c97589471b5f4312acac4e396a250ee7158c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 24 Jul 2019 18:41:39 +0200 Subject: [PATCH 04/12] Add a simple example for Spartan 6 --- examples/mimas2/README | 8 ++++++++ examples/mimas2/example.ucf | 13 +++++++++++++ examples/mimas2/example.v | 14 ++++++++++++++ examples/mimas2/run.sh | 8 ++++++++ examples/mimas2/run_yosys.ys | 4 ++++ 5 files changed, 47 insertions(+) create mode 100644 examples/mimas2/README create mode 100644 examples/mimas2/example.ucf create mode 100644 examples/mimas2/example.v create mode 100644 examples/mimas2/run.sh create mode 100644 examples/mimas2/run_yosys.ys diff --git a/examples/mimas2/README b/examples/mimas2/README new file mode 100644 index 000000000..b12875cbc --- /dev/null +++ b/examples/mimas2/README @@ -0,0 +1,8 @@ +A simple example design, based on the Numato Labs Mimas V2 board +================================================================ + +This example uses Yosys for synthesis and Xilinx ISE +for place&route and bit-stream creation. + +To synthesize: + bash run.sh diff --git a/examples/mimas2/example.ucf b/examples/mimas2/example.ucf new file mode 100644 index 000000000..4e31b74ab --- /dev/null +++ b/examples/mimas2/example.ucf @@ -0,0 +1,13 @@ +CONFIG VCCAUX = "3.3" ; + + +NET "CLK" LOC = D9 | IOSTANDARD = LVCMOS33 | PERIOD = 12MHz ; + +NET "LED[7]" LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "LED[6]" LOC = P16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "LED[5]" LOC = N15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "LED[4]" LOC = N16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "LED[3]" LOC = U17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "LED[2]" LOC = U18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "LED[1]" LOC = T17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +NET "LED[0]" LOC = T18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; diff --git a/examples/mimas2/example.v b/examples/mimas2/example.v new file mode 100644 index 000000000..2a9117393 --- /dev/null +++ b/examples/mimas2/example.v @@ -0,0 +1,14 @@ +module example( + input wire CLK, + output wire [7:0] LED +); + +reg [27:0] ctr; +initial ctr = 0; + +always @(posedge CLK) + ctr <= ctr + 1; + +assign LED = ctr[27:20]; + +endmodule diff --git a/examples/mimas2/run.sh b/examples/mimas2/run.sh new file mode 100644 index 000000000..aafde78ed --- /dev/null +++ b/examples/mimas2/run.sh @@ -0,0 +1,8 @@ +#!/bin/sh +set -e +yosys run_yosys.ys +edif2ngd example.edif +ngdbuild example -uc example.ucf -p xc6slx9csg324-3 +map -w example +par -w example.ncd example_par.ncd +bitgen -w example_par.ncd -g StartupClk:JTAGClk diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys new file mode 100644 index 000000000..b3204b1ca --- /dev/null +++ b/examples/mimas2/run_yosys.ys @@ -0,0 +1,4 @@ +read_verilog example.v +synth_xilinx -top example -family xc6s +iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I +write_edif -pvector bra example.edif From ab607e896e9f5faff939b4395b01344a36e9fc1b Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 25 Jul 2019 08:19:07 +0100 Subject: [PATCH 05/12] xilinx: Fix missing cell name underscore in cells_map.v Signed-off-by: David Shah --- techlibs/xilinx/cells_map.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 2eb9fa2c1..b8e5bafc7 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -24,9 +24,9 @@ module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLA (* techmap_celltype = "$_DFF_PN0_" *) module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule (* techmap_celltype = "$_DFF_NN1_" *) -module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule (* techmap_celltype = "$_DFF_PN1_" *) -module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; From 70882a807074a521515d1525d83ed7321f982d7e Mon Sep 17 00:00:00 2001 From: Jakob Wenzel Date: Thu, 25 Jul 2019 09:51:09 +0200 Subject: [PATCH 06/12] replaced std::iterator with using statements --- kernel/rtlil.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 10225cff2..712250b3e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -420,12 +420,12 @@ namespace RTLIL // It maintains a reference counter that is used to make sure that the container is not modified while being iterated over. template - struct ObjIterator : public std::iterator - { + struct ObjIterator { + using iterator_category = std::forward_iterator_tag; + using value_type = T; + using difference_type = ptrdiff_t; + using pointer = T*; + using reference = T&; typename dict::iterator it; dict *list_p; int *refcount_p; From c5e31ac9c3c49f38ddcb6e613ef4a092d69f71a2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Jul 2019 10:44:20 -0700 Subject: [PATCH 07/12] Bump abc to fix &mfs bug --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d33f27b63..3bc119800 100644 --- a/Makefile +++ b/Makefile @@ -122,7 +122,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = 62487de +ABCREV = 5776ad0 ABCPULL = 1 ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 From 933db0410e096286c21772f5a2f44b03d2ed0b57 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 26 Jul 2019 10:23:58 +0100 Subject: [PATCH 08/12] Add support for reading gzip'd input files Signed-off-by: David Shah --- .travis.yml | 5 ++++ Makefile | 7 ++++++ README.md | 6 ++--- kernel/register.cc | 40 ++++++++++++++++++++++++++++++++ tests/various/gzip_verilog.v.gz | Bin 0 -> 82 bytes tests/various/gzip_verilog.ys | 2 ++ 6 files changed, 57 insertions(+), 3 deletions(-) create mode 100644 tests/various/gzip_verilog.v.gz create mode 100644 tests/various/gzip_verilog.ys diff --git a/.travis.yml b/.travis.yml index 957735f1d..4102f05fe 100644 --- a/.travis.yml +++ b/.travis.yml @@ -36,6 +36,7 @@ matrix: - libboost-system-dev - libboost-python-dev - libboost-filesystem-dev + - zlib1g-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8" @@ -64,6 +65,7 @@ matrix: - libboost-system-dev - libboost-python-dev - libboost-filesystem-dev + - zlib1g-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-6 && CXX=g++-6" @@ -92,6 +94,7 @@ matrix: - libboost-system-dev - libboost-python-dev - libboost-filesystem-dev + - zlib1g-dev env: - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7" @@ -121,6 +124,7 @@ matrix: - libboost-system-dev - libboost-python-dev - libboost-filesystem-dev + - zlib1g-dev env: - MATRIX_EVAL="CONFIG=clang && CC=clang-3.8 && CXX=clang++-3.8" @@ -149,6 +153,7 @@ matrix: - libboost-system-dev - libboost-python-dev - libboost-filesystem-dev + - zlib1g-dev env: - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0" diff --git a/Makefile b/Makefile index d33f27b63..ea804e0d5 100644 --- a/Makefile +++ b/Makefile @@ -19,6 +19,7 @@ ENABLE_VERIFIC := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_PROTOBUF := 0 +ENABLE_ZLIB := 1 # python wrappers ENABLE_PYOSYS := 0 @@ -384,6 +385,12 @@ ifeq ($(ENABLE_GLOB),1) CXXFLAGS += -DYOSYS_ENABLE_GLOB endif +ifeq ($(ENABLE_ZLIB),1) +CXXFLAGS += -DYOSYS_ENABLE_ZLIB +LDLIBS += -lz +endif + + ifeq ($(ENABLE_TCL),1) TCL_VERSION ?= tcl$(shell bash -c "tclsh <(echo 'puts [info tclversion]')") ifeq ($(OS), FreeBSD) diff --git a/README.md b/README.md index 9e221be38..2a7081304 100644 --- a/README.md +++ b/README.md @@ -67,13 +67,13 @@ prerequisites for building yosys: $ sudo apt-get install build-essential clang bison flex \ libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 libboost-system-dev \ - libboost-python-dev libboost-filesystem-dev + libboost-python-dev libboost-filesystem-dev zlib1g-dev Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies: $ brew tap Homebrew/bundle && brew bundle $ sudo port install bison flex readline gawk libffi \ - git graphviz pkgconfig python36 boost + git graphviz pkgconfig python36 boost zlib On FreeBSD use the following command to install all prerequisites: @@ -85,7 +85,7 @@ On FreeBSD system use gmake instead of make. To run tests use: For Cygwin use the following command to install all prerequisites, or select these additional packages: - setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build + setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well as a source distribution for Visual Studio. Visit the Yosys download page for diff --git a/kernel/register.cc b/kernel/register.cc index 26da96b95..4f1501330 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -25,6 +25,26 @@ #include #include +#ifdef YOSYS_ENABLE_ZLIB +#include + +PRIVATE_NAMESPACE_BEGIN +#define GZ_BUFFER_SIZE 8192 +void decompress_gzip(const std::string &filename, std::stringstream &out) +{ + char buffer[GZ_BUFFER_SIZE]; + int bytes_read; + gzFile gzf = gzopen(filename.c_str(), "rb"); + while(!gzeof(gzf)) { + bytes_read = gzread(gzf, reinterpret_cast(buffer), GZ_BUFFER_SIZE); + out.write(buffer, bytes_read); + } + gzclose(gzf); +} +PRIVATE_NAMESPACE_END + +#endif + YOSYS_NAMESPACE_BEGIN #define MAX_REG_COUNT 1000 @@ -436,6 +456,26 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector(magic), 3); + if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { +#ifdef YOSYS_ENABLE_ZLIB + log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); + if (magic[2] != 8) + log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n", + filename.c_str(), unsigned(magic[2])); + delete ff; + std::stringstream *df = new std::stringstream(); + decompress_gzip(filename, *df); + f = df; +#else + log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str()); +#endif + } else { + ff->clear(); + ff->seekg(0, std::ios::beg); + } } if (f == NULL) log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); diff --git a/tests/various/gzip_verilog.v.gz b/tests/various/gzip_verilog.v.gz new file mode 100644 index 0000000000000000000000000000000000000000..c52a95358046dad231d5efe9103ce7e919b707a1 GIT binary patch literal 82 zcmb2|=HSpjY8A`CoL-e#5MP#Bl$n#Cu2;rz`mDd^S-h> literal 0 HcmV?d00001 diff --git a/tests/various/gzip_verilog.ys b/tests/various/gzip_verilog.ys new file mode 100644 index 000000000..870317e80 --- /dev/null +++ b/tests/various/gzip_verilog.ys @@ -0,0 +1,2 @@ +read_verilog gzip_verilog.v.gz +select -assert-any top From da6701c4cd26d559241c8a3de61b51ace1e03fe4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 26 Jul 2019 10:29:05 +0100 Subject: [PATCH 09/12] Fix frontend auto-detection for gzipped input Signed-off-by: David Shah --- kernel/yosys.cc | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index a42a7c0b8..191b6d5c7 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -894,23 +894,26 @@ void run_frontend(std::string filename, std::string command, std::string *backen design = yosys_design; if (command == "auto") { - if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") + std::string filename_trim = filename; + if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".gz") + filename_trim.erase(filename_trim.size()-3); + if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-2) == ".v") command = "verilog"; - else if (filename.size() > 2 && filename.substr(filename.size()-3) == ".sv") + else if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-3) == ".sv") command = "verilog -sv"; - else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".vhd") + else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".vhd") command = "vhdl"; - else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif") + else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".blif") command = "blif"; - else if (filename.size() > 5 && filename.substr(filename.size()-6) == ".eblif") + else if (filename_trim.size() > 5 && filename_trim.substr(filename_trim.size()-6) == ".eblif") command = "blif"; - else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".json") + else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".json") command = "json"; - else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") + else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".il") command = "ilang"; - else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".ys") + else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".ys") command = "script"; - else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".tcl") + else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".tcl") command = "tcl"; else if (filename == "-") command = "script"; From 92694ea3a997cc6d081b6896c213d308adb466d5 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 26 Jul 2019 13:35:39 +0100 Subject: [PATCH 10/12] verilog_lexer: Increase YY_BUF_SIZE to 65536 Signed-off-by: David Shah --- frontends/verilog/verilog_lexer.l | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 951d9c66f..57e55b1f4 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -70,6 +70,9 @@ YOSYS_NAMESPACE_END #define YY_INPUT(buf,result,max_size) \ result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size) +#undef YY_BUF_SIZE +#define YY_BUF_SIZE 65536 + %} %option yylineno From 482926cbd306cc71aebb81b1b8e825ced9b3f26d Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 26 Jul 2019 15:53:21 +0100 Subject: [PATCH 11/12] Update CHANGELOG Signed-off-by: David Shah --- CHANGELOG | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 44d83c1bf..00b10c591 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -14,7 +14,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth -abc9" (experimental) - Added "script -scriptwire - "synth_xilinx" to now infer wide multiplexers (-widemux to enable) - + - Added automatic gzip decompression for frontends Yosys 0.8 .. Yosys 0.8-dev -------------------------- From 3e4307c104f5caf0f3449421a75b19e7c90a71fe Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 29 Jul 2019 12:29:13 +0200 Subject: [PATCH 12/12] Fix case when file does not exist --- kernel/register.cc | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/kernel/register.cc b/kernel/register.cc index 4f1501330..4c6e3591f 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -456,25 +456,27 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector(magic), 3); - if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { -#ifdef YOSYS_ENABLE_ZLIB - log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); - if (magic[2] != 8) - log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n", - filename.c_str(), unsigned(magic[2])); - delete ff; - std::stringstream *df = new std::stringstream(); - decompress_gzip(filename, *df); - f = df; -#else - log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str()); -#endif - } else { - ff->clear(); - ff->seekg(0, std::ios::beg); + if (f != NULL) { + // Check for gzip magic + unsigned char magic[3]; + int n = readsome(*ff, reinterpret_cast(magic), 3); + if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { + #ifdef YOSYS_ENABLE_ZLIB + log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); + if (magic[2] != 8) + log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n", + filename.c_str(), unsigned(magic[2])); + delete ff; + std::stringstream *df = new std::stringstream(); + decompress_gzip(filename, *df); + f = df; + #else + log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str()); + #endif + } else { + ff->clear(); + ff->seekg(0, std::ios::beg); + } } } if (f == NULL)