Merge pull request #1 from mschmoelzer/master

Add support for "fsm_export" synthesis attributes to fsm_export pass
This commit is contained in:
Clifford Wolf 2013-01-08 02:20:24 -08:00
commit e8231ee46b
1 changed files with 86 additions and 46 deletions

View File

@ -29,7 +29,7 @@
#include <fstream> #include <fstream>
/** /**
* Convert signal into a KISS-compatible textual representation. * Convert a signal into a KISS-compatible textual representation.
*/ */
std::string kiss_convert_signal(const RTLIL::SigSpec &sig) { std::string kiss_convert_signal(const RTLIL::SigSpec &sig) {
if (!sig.is_fully_const()) { if (!sig.is_fully_const()) {
@ -40,43 +40,46 @@ std::string kiss_convert_signal(const RTLIL::SigSpec &sig) {
} }
/** /**
* Exports each Finite State Machine (FSM) in the design to a file in KISS2 format. * Create a KISS2 file from a cell.
*
* The destination file name is taken from the fsm_export attribute if present,
* e.g. (* fsm_export="filename.kiss2" *). If this attribute is not present,
* the file name will be assembled from the module and cell names.
*
* @param module pointer to module which contains the FSM cell.
* @param cell pointer to the FSM cell which should be exported.
*/ */
struct FsmExportPass : public Pass { void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell) {
FsmExportPass() : Pass("fsm_export") { std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
FsmData fsm_data; FsmData fsm_data;
std::string kiss_name;
std::ofstream kiss_file;
size_t i;
FsmData::transition_t tr; FsmData::transition_t tr;
std::ofstream kiss_file;
std::string kiss_name;
size_t i;
log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n"); attr_it = cell->attributes.find("\\fsm_export");
extra_args(args, 1, design); if (attr_it != cell->attributes.end() && attr_it->second.str != "") {
kiss_name.assign(attr_it->second.str);
for (auto &mod_it : design->modules) }
for (auto &cell_it : mod_it.second->cells) else {
if (cell_it.second->type == "$fsm") { kiss_name.assign(module->name);
kiss_name.assign(mod_it.first.c_str()); kiss_name.append('-' + cell->name + ".kiss2");
kiss_name.append("-" + cell_it.second->name + ".kiss2"); }
fsm_data.copy_from_cell(cell_it.second);
log("\n"); log("\n");
log("Exporting FSM `%s' from module `%s' to file `%s'.\n", log("Exporting FSM `%s' from module `%s' to file `%s'.\n",
cell_it.second->name.c_str(), cell->name.c_str(),
mod_it.first.c_str(), module->name.c_str(),
kiss_name.c_str()); kiss_name.c_str());
kiss_file.open(kiss_name, std::ios::out | std::ios::trunc); kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
if (!kiss_file.is_open()) { if (!kiss_file.is_open()) {
log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str()); log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str());
return;
} }
fsm_data.copy_from_cell(cell);
kiss_file << ".start_kiss" << std::endl; kiss_file << ".start_kiss" << std::endl;
kiss_file << ".i " << std::dec << fsm_data.num_inputs << std::endl; kiss_file << ".i " << std::dec << fsm_data.num_inputs << std::endl;
kiss_file << ".o " << std::dec << fsm_data.num_outputs << std::endl; kiss_file << ".o " << std::dec << fsm_data.num_outputs << std::endl;
@ -92,6 +95,7 @@ struct FsmExportPass : public Pass {
kiss_file << kiss_convert_signal(tr.ctrl_out) << std::endl; kiss_file << kiss_convert_signal(tr.ctrl_out) << std::endl;
} }
catch (int) { catch (int) {
kiss_file.close();
log_error("exporting an FSM input or output signal failed.\n"); log_error("exporting an FSM input or output signal failed.\n");
} }
} }
@ -99,5 +103,41 @@ struct FsmExportPass : public Pass {
kiss_file << ".end_kiss" << std::endl << ".end" << std::endl; kiss_file << ".end_kiss" << std::endl << ".end" << std::endl;
kiss_file.close(); kiss_file.close();
} }
/**
* Exports Finite State Machines in the design to one file per FSM. Currently,
* only the KISS2 file format is supported.
*/
struct FsmExportPass : public Pass {
FsmExportPass() : Pass("fsm_export") {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
std::string arg;
bool flag_noauto = false;
size_t argidx;
log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
for (argidx = 1; argidx < args.size(); argidx++) {
arg = args[argidx];
if (arg == "-noauto") {
flag_noauto = true;
continue;
}
break;
}
extra_args(args, argidx, design);
for (auto &mod_it : design->modules)
for (auto &cell_it : mod_it.second->cells)
if (cell_it.second->type == "$fsm") {
attr_it = cell_it.second->attributes.find("\\fsm_export");
if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) {
write_kiss2(mod_it.second, cell_it.second);
}
}
} }
} FsmExportPass; } FsmExportPass;