Merge branch 'master' of github.com:cliffordwolf/yosys

backends/json/json.cc

@@ -411,10 +411,10 @@ struct JsonBackend : public Backend {
 		log("      - the inverted value of the specified input port bit\n");
 		log("\n");
 		log("    [ \"and\", <node-index>, <node-index>, <out-list> ]\n");
-		log("      - the ANDed value of the speciefied nodes\n");
+		log("      - the ANDed value of the specified nodes\n");
 		log("\n");
 		log("    [ \"nand\", <node-index>, <node-index>, <out-list> ]\n");
-		log("      - the inverted ANDed value of the speciefied nodes\n");
+		log("      - the inverted ANDed value of the specified nodes\n");
 		log("\n");
 		log("    [ \"true\", <out-list> ]\n");
 		log("      - the constant value 1\n");
@@ -445,7 +445,7 @@ struct JsonBackend : public Backend {
 		log("    ]\n");
 		log("\n");
 		log("Future version of Yosys might add support for additional fields in the JSON\n");
-		log("format. A program processing this format must ignore all unkown fields.\n");
+		log("format. A program processing this format must ignore all unknown fields.\n");
 		log("\n");
 	}
 	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)

backends/spice/spice.cc

@@ -27,13 +27,33 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
+static string spice_id2str(IdString id)
+{
+	static const char *escape_chars = "$\\[]()<>";
+	string s = RTLIL::unescape_id(id);
+
+	for (auto &ch : s)
+		if (strchr(escape_chars, ch) != nullptr) ch = '_';
+
+	return s;
+}
+
+static string spice_id2str(IdString id, bool use_inames, idict<IdString, 1> &inums)
+{
+	if (!use_inames && *id.c_str() == '$')
+		return stringf("%d", inums(id));
+	return spice_id2str(id);
+}
+
+static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter, bool use_inames, idict<IdString, 1> &inums)
 {
 	if (s.wire) {
+		if (s.wire->port_id)
+			use_inames = true;
 		if (s.wire->width > 1)
-			f << stringf(" %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset);
+			f << stringf(" %s.%d", spice_id2str(s.wire->name, use_inames, inums).c_str(), s.offset);
 		else
-			f << stringf(" %s", RTLIL::id2cstr(s.wire->name));
+			f << stringf(" %s", spice_id2str(s.wire->name, use_inames, inums).c_str());
 	} else {
 		if (s == RTLIL::State::S0)
 			f << stringf(" %s", neg.c_str());
@@ -44,9 +64,10 @@ static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg,
 	}
 }
 
-static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian)
+static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian, bool use_inames)
 {
 	SigMap sigmap(module);
+	idict<IdString, 1> inums;
 	int cell_counter = 0, conn_counter = 0, nc_counter = 0;
 
 	for (auto &cell_it : module->cells_)
@@ -59,7 +80,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 		if (design->modules_.count(cell->type) == 0)
 		{
 			log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
-					RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
+					log_id(cell->type), log_id(module), log_id(cell));
 			for (auto &conn : cell->connections()) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				port_sigs.push_back(sig);
@@ -93,18 +114,18 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 		for (auto &sig : port_sigs) {
 			for (int i = 0; i < sig.size(); i++) {
 				RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1);
-				print_spice_net(f, s, neg, pos, ncpf, nc_counter);
+				print_spice_net(f, s, neg, pos, ncpf, nc_counter, use_inames, inums);
 			}
 		}
 
-		f << stringf(" %s\n", RTLIL::id2cstr(cell->type));
+		f << stringf(" %s\n", spice_id2str(cell->type).c_str());
 	}
 
 	for (auto &conn : module->connections())
 	for (int i = 0; i < conn.first.size(); i++) {
 		f << stringf("V%d", conn_counter++);
-		print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter);
+		print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter, use_inames, inums);
-		print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter);
+		print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter, use_inames, inums);
 		f << stringf(" DC 0\n");
 	}
 }
@@ -132,6 +153,10 @@ struct SpiceBackend : public Backend {
 		log("    -nc_prefix\n");
 		log("        prefix for not-connected nets (default: _NC)\n");
 		log("\n");
+		log("    -inames\n");
+		log("        include names of internal ($-prefixed) nets in outputs\n");
+		log("        (default is to use net numbers instead)\n");
+		log("\n");
 		log("    -top top_module\n");
 		log("        set the specified module as design top module\n");
 		log("\n");
@@ -140,7 +165,7 @@ struct SpiceBackend : public Backend {
 	{
 		std::string top_module_name;
 		RTLIL::Module *top_module = NULL;
-		bool big_endian = false;
+		bool big_endian = false, use_inames = false;
 		std::string neg = "Vss", pos = "Vdd", ncpf = "_NC";
 
 		log_header("Executing SPICE backend.\n");
@@ -152,6 +177,10 @@ struct SpiceBackend : public Backend {
 				big_endian = true;
 				continue;
 			}
+			if (args[argidx] == "-inames") {
+				use_inames = true;
+				continue;
+			}
 			if (args[argidx] == "-neg" && argidx+1 < args.size()) {
 				neg = args[++argidx];
 				continue;
@@ -187,9 +216,9 @@ struct SpiceBackend : public Backend {
 				continue;
 
 			if (module->processes.size() != 0)
-				log_error("Found unmapped processes in module %s: unmapped processes are not supported in SPICE backend!\n", RTLIL::id2cstr(module->name));
+				log_error("Found unmapped processes in module %s: unmapped processes are not supported in SPICE backend!\n", log_id(module));
 			if (module->memories.size() != 0)
-				log_error("Found munmapped emories in module %s: unmapped memories are not supported in SPICE backend!\n", RTLIL::id2cstr(module->name));
+				log_error("Found munmapped emories in module %s: unmapped memories are not supported in SPICE backend!\n", log_id(module));
 
 			if (module->name == RTLIL::escape_id(top_module_name)) {
 				top_module = module;
@@ -206,24 +235,24 @@ struct SpiceBackend : public Backend {
 				ports.at(wire->port_id-1) = wire;
 			}
 
-			*f << stringf(".SUBCKT %s", RTLIL::id2cstr(module->name));
+			*f << stringf(".SUBCKT %s", spice_id2str(module->name).c_str());
 			for (RTLIL::Wire *wire : ports) {
 				log_assert(wire != NULL);
 				if (wire->width > 1) {
 					for (int i = 0; i < wire->width; i++)
-						*f << stringf(" %s[%d]", RTLIL::id2cstr(wire->name), big_endian ? wire->width - 1 - i : i);
+						*f << stringf(" %s.%d", spice_id2str(wire->name).c_str(), big_endian ? wire->width - 1 - i : i);
 				} else
-					*f << stringf(" %s", RTLIL::id2cstr(wire->name));
+					*f << stringf(" %s", spice_id2str(wire->name).c_str());
 			}
 			*f << stringf("\n");
-			print_spice_module(*f, module, design, neg, pos, ncpf, big_endian);
+			print_spice_module(*f, module, design, neg, pos, ncpf, big_endian, use_inames);
-			*f << stringf(".ENDS %s\n\n", RTLIL::id2cstr(module->name));
+			*f << stringf(".ENDS %s\n\n", spice_id2str(module->name).c_str());
 		}
 
 		if (!top_module_name.empty()) {
 			if (top_module == NULL)
 				log_error("Can't find top module `%s'!\n", top_module_name.c_str());
-			print_spice_module(*f, top_module, design, neg, pos, ncpf, big_endian);
+			print_spice_module(*f, top_module, design, neg, pos, ncpf, big_endian, use_inames);
 			*f << stringf("\n");
 		}
 

examples/cmos/cmos_cells_digital.sp

@@ -0,0 +1,31 @@
+
+.SUBCKT BUF A Y
+.model buffer1 d_buffer
+Abuf A Y buffer1
+.ENDS NOT
+
+.SUBCKT NOT A Y
+.model not1 d_inverter
+Anot A Y not1
+.ENDS NOT
+
+.SUBCKT NAND A B Y
+.model nand1 d_nand
+Anand [A B] Y nand1
+.ENDS NAND
+
+.SUBCKT NOR A B Y
+.model nor1 d_nor
+Anand [A B] Y nor1
+.ENDS NOR
+
+.SUBCKT DLATCH E D Q
+.model latch1 d_latch
+Alatch D E null null Q nQ latch1
+.ENDS DLATCH
+
+.SUBCKT DFF C D Q
+.model dff1 d_dff
+Adff D C null null Q nQ dff1
+.ENDS DFF
+

examples/cmos/testbench.sh

@@ -5,3 +5,6 @@ set -ex
 ../../yosys counter.ys
 ngspice testbench.sp
 
+# requires ngspice with xspice support enabled:
+#ngspice testbench_digital.sp
+

examples/cmos/testbench.sp

@@ -9,8 +9,8 @@ Vdd Vdd 0 DC 3
 .MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
 
 * load design and library
-.include synth.sp
 .include cmos_cells.sp
+.include synth.sp
 
 * input signals
 Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)

examples/cmos/testbench_digital.sp

@@ -0,0 +1,35 @@
+
+* supply voltages
+.global Vss Vdd
+Vss Vss 0 DC 0
+Vdd Vdd 0 DC 3
+
+* simple transistor model
+.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
+
+* load design and library
+.include cmos_cells_digital.sp
+.include synth.sp
+
+* input signals
+Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)
+Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40)
+Ven  en  0 PULSE(0 3 0.5 0.1 0.1 5.9 8)
+
+Xuut dclk drst den dout0 dout1 dout2 counter
+* Bridge to digital
+.model adc_buff adc_bridge(in_low = 0.8 in_high=2)
+.model dac_buff dac_bridge(out_high = 3.5)
+Aad [clk rst en] [dclk drst den] adc_buff
+Ada [dout0 dout1 dout2] [out0 out1 out2] dac_buff
+
+
+.tran 0.01 50
+
+.control
+run
+plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30
+.endc
+
+.end

manual/command-reference-manual.tex

@@ -3783,10 +3783,10 @@ The following node-types may be used:
       - the inverted value of the specified input port bit
 
     [ "and", <node-index>, <node-index>, <out-list> ]
-      - the ANDed value of the speciefied nodes
+      - the ANDed value of the specified nodes
 
     [ "nand", <node-index>, <node-index>, <out-list> ]
-      - the inverted ANDed value of the speciefied nodes
+      - the inverted ANDed value of the specified nodes
 
     [ "true", <out-list> ]
       - the constant value 1
@@ -3817,7 +3817,7 @@ inferred by the following code:
     ]
 
 Future version of Yosys might add support for additional fields in the JSON
-format. A program processing this format must ignore all unkown fields.
+format. A program processing this format must ignore all unknown fields.
 \end{lstlisting}
 
 \section{write\_smt2 -- write design to SMT-LIBv2 file}