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CIs before PIs; also sort each cell's connections before iterating

This commit is contained in:
Eddie Hung 2019-04-16 16:37:47 -07:00
parent b015ed48f7
commit e7a8955818
1 changed files with 7 additions and 5 deletions
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12
backends/aiger/xaiger.cc
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@ -215,6 +215,7 @@ struct XAigerWriter
RTLIL::Module* box_module = module->design->module(cell->type); RTLIL::Module* box_module = module->design->module(cell->type);
bool abc_box = box_module && box_module->attributes.count("\\abc_box_id"); bool abc_box = box_module && box_module->attributes.count("\\abc_box_id");
cell->connections_.sort(RTLIL::sort_by_id_str());
for (const auto &c : cell->connections()) { for (const auto &c : cell->connections()) {
/*if (c.second.is_fully_const()) continue;*/ /*if (c.second.is_fully_const()) continue;*/
for (auto b : c.second.bits()) { for (auto b : c.second.bits()) {
@ -313,17 +314,17 @@ struct XAigerWriter
aig_map[State::S0] = 0; aig_map[State::S0] = 0;
aig_map[State::S1] = 1; aig_map[State::S1] = 1;
for (auto bit : input_bits) {
aig_m++, aig_i++;
aig_map[bit] = 2*aig_m;
}
for (auto &c : ci_bits) { for (auto &c : ci_bits) {
aig_m++, aig_i++; aig_m++, aig_i++;
c.second = 2*aig_m; c.second = 2*aig_m;
aig_map[c.first] = c.second; aig_map[c.first] = c.second;
} }
for (auto bit : input_bits) {
aig_m++, aig_i++;
aig_map[bit] = 2*aig_m;
}
if (imode && input_bits.empty()) { if (imode && input_bits.empty()) {
aig_m++, aig_i++; aig_m++, aig_i++;
} }
@ -585,6 +586,7 @@ struct XAigerWriter
holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type); holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
RTLIL::Wire *holes_wire; RTLIL::Wire *holes_wire;
int num_inputs = 0; int num_inputs = 0;
// NB: cell->connections_ already sorted from before
for (const auto &c : cell->connections()) { for (const auto &c : cell->connections()) {
if (cell->input(c.first)) { if (cell->input(c.first)) {
box_inputs += c.second.size(); box_inputs += c.second.size();