mirror of https://github.com/YosysHQ/yosys.git
read_aiger to create sane $lut names, and rename when renaming driving wire
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0b1fc46ae3
commit
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@ -322,7 +322,7 @@ void AigerReader::parse_xaiger()
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RTLIL::Cell *output_cell = module->cell(stringf("\\n%d_and", rootNodeID));
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RTLIL::Cell *output_cell = module->cell(stringf("\\n%d_and", rootNodeID));
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log_assert(output_cell);
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log_assert(output_cell);
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module->remove(output_cell);
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module->remove(output_cell);
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module->addLut(NEW_ID, input_sig, output_sig, std::move(lut_mask));
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module->addLut(stringf("\\n%d_lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
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}
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}
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}
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}
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else if (c == 'n') {
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else if (c == 'n') {
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@ -346,6 +346,10 @@ void AigerReader::parse_xaiger()
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else log_abort();
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else log_abort();
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module->rename(wire, stringf("\\%s", s.c_str()));
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module->rename(wire, stringf("\\%s", s.c_str()));
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RTLIL::Cell* driver = module->cell(stringf("%s_lut", wire->name.c_str()));
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module->rename(driver, stringf("%s_lut", wire->name.c_str()));
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std::getline(f, line); // Ignore up to start of next line
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std::getline(f, line); // Ignore up to start of next line
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++line_count;
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++line_count;
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}
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}
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@ -384,6 +388,8 @@ void AigerReader::parse_xaiger()
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continue;
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continue;
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log_assert(wire->port_output);
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log_assert(wire->port_output);
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RTLIL::Cell* driver = module->cell(stringf("%s_lut", wire->name.c_str()));
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if (index == 0)
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if (index == 0)
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module->rename(wire, RTLIL::escape_id(symbol));
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module->rename(wire, RTLIL::escape_id(symbol));
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else if (index > 0) {
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else if (index > 0) {
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@ -391,6 +397,9 @@ void AigerReader::parse_xaiger()
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if (wideports)
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if (wideports)
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wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index);
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wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index);
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}
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}
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if (driver)
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module->rename(driver, stringf("%s_lut", wire->name.c_str()));
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}
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}
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else
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else
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log_error("Symbol type '%s' not recognised.\n", type.c_str());
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log_error("Symbol type '%s' not recognised.\n", type.c_str());
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@ -440,7 +449,7 @@ void AigerReader::parse_xaiger()
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module->fixup_ports();
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module->fixup_ports();
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design->add(module);
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design->add(module);
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Pass::call(design, "clean");
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Pass::call(design, "clean -purge");
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}
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}
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void AigerReader::parse_aiger_ascii()
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void AigerReader::parse_aiger_ascii()
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