mirror of https://github.com/YosysHQ/yosys.git
greenpak4: Added GP_PGEN cell definition
This commit is contained in:
parent
091d32b563
commit
e78fa157a3
|
@ -305,6 +305,27 @@ module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
|
||||||
|
initial OUT = 0;
|
||||||
|
parameter PATTERN_DATA = 16'h0;
|
||||||
|
parameter PATTERN_LEN = 4'd16;
|
||||||
|
|
||||||
|
reg[3:0] count = 0;
|
||||||
|
always @(posedge CLK) begin
|
||||||
|
if(!nRST)
|
||||||
|
OUT <= PATTERN_DATA[0];
|
||||||
|
|
||||||
|
else begin
|
||||||
|
count <= count + 1;
|
||||||
|
OUT <= PATTERN_DATA[count];
|
||||||
|
|
||||||
|
if( (count + 1) == PATTERN_LEN)
|
||||||
|
count <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
module GP_POR(output reg RST_DONE);
|
module GP_POR(output reg RST_DONE);
|
||||||
parameter POR_TIME = 500;
|
parameter POR_TIME = 500;
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue