From 7bd1c664a6f0d9a20a2f3f0c0f136403918afacf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 10:51:02 -0700
Subject: [PATCH 01/32] Initial adaptation of muxpack from shregmap

---
 passes/techmap/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index cf9e198ad..561636080 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -37,6 +37,7 @@ OBJS += passes/techmap/attrmap.o
 OBJS += passes/techmap/zinit.o
 OBJS += passes/techmap/dff2dffs.o
 OBJS += passes/techmap/flowmap.o
+OBJS += passes/techmap/muxpack.o
 endif
 
 GENFILES += passes/techmap/techmap.inc

From 543dd11c7e46f9c88bd1f0d21474bac95d1ab6d1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 11:03:45 -0700
Subject: [PATCH 02/32] Missing file

---
 passes/techmap/muxpack.cc | 232 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 232 insertions(+)
 create mode 100644 passes/techmap/muxpack.cc

diff --git a/passes/techmap/muxpack.cc b/passes/techmap/muxpack.cc
new file mode 100644
index 000000000..4945affb0
--- /dev/null
+++ b/passes/techmap/muxpack.cc
@@ -0,0 +1,232 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct MuxpackWorker
+{
+	Module *module;
+	SigMap sigmap;
+
+	int mux_count, pmux_count;
+
+	pool<Cell*> remove_cells;
+
+	dict<SigSpec, Cell*> sig_chain_next;
+	dict<SigSpec, Cell*> sig_chain_prev;
+	pool<SigBit> sigbit_with_non_chain_users;
+	pool<Cell*> chain_start_cells;
+
+	void make_sig_chain_next_prev()
+	{
+		for (auto wire : module->wires())
+		{
+			if (wire->port_output || wire->get_bool_attribute("\\keep")) {
+				for (auto bit : sigmap(wire)) {
+					sigbit_with_non_chain_users.insert(bit);
+                }
+			}
+		}
+
+		for (auto cell : module->cells())
+		{
+			if (cell->type.in("$mux") && !cell->get_bool_attribute("\\keep"))
+			{
+				SigSpec a_sig = sigmap(cell->getPort("\\A"));
+				SigSpec y_sig = sigmap(cell->getPort("\\Y"));
+   
+				if (sig_chain_next.count(a_sig))
+                    for (auto a_bit : a_sig.bits())
+                        sigbit_with_non_chain_users.insert(a_bit);
+                else
+					sig_chain_next[a_sig] = cell;
+
+				sig_chain_prev[y_sig] = cell;
+                continue;
+			}
+
+			for (auto conn : cell->connections())
+				if (cell->input(conn.first))
+					for (auto bit : sigmap(conn.second))
+						sigbit_with_non_chain_users.insert(bit);
+		}
+	}
+
+	void find_chain_start_cells()
+	{
+		for (auto it : sig_chain_next)
+		{
+            for (auto bit : it.first.bits())
+                if (sigbit_with_non_chain_users.count(bit))
+                    goto start_cell;
+
+			if (sig_chain_prev.count(it.first) != 0)
+			{
+				Cell *c1 = sig_chain_prev.at(it.first);
+				Cell *c2 = it.second;
+
+				if (c1->type != c2->type)
+					goto start_cell;
+
+				if (c1->parameters != c2->parameters)
+					goto start_cell;
+
+				continue;
+			}
+
+		start_cell:
+			chain_start_cells.insert(it.second);
+		}
+	}
+
+	vector<Cell*> create_chain(Cell *start_cell)
+	{
+		vector<Cell*> chain;
+
+		Cell *c = start_cell;
+		while (c != nullptr)
+		{
+			chain.push_back(c);
+
+			SigSpec y_sig = sigmap(c->getPort("\\Y"));
+
+			if (sig_chain_next.count(y_sig) == 0)
+				break;
+
+			c = sig_chain_next.at(y_sig);
+			if (chain_start_cells.count(c) != 0)
+				break;
+		}
+
+		return chain;
+	}
+
+	void process_chain(vector<Cell*> &chain)
+	{
+		if (GetSize(chain) < 2)
+			return;
+
+		int cursor = 0;
+		while (cursor < GetSize(chain))
+		{
+			int cases = GetSize(chain) - cursor;
+
+			Cell *first_cell = chain[cursor];
+			dict<int, SigBit> taps_dict;
+
+			if (cases < 2) {
+				cursor++;
+				continue;
+			}
+
+			Cell *last_cell = chain[cursor+cases-1];
+
+			log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
+				log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases);
+
+			mux_count += cases;
+			pmux_count += 1;
+
+			first_cell->type = "$pmux";
+            SigSpec b_sig = first_cell->getPort("\\B");
+            SigSpec s_sig = first_cell->getPort("\\S");
+
+			for (int i = 1; i < cases; i++) {
+                Cell* cursor_cell = chain[cursor+i];
+                b_sig.append(cursor_cell->getPort("\\B"));
+                s_sig.append(cursor_cell->getPort("\\S"));
+				remove_cells.insert(cursor_cell);
+            }
+
+			first_cell->setPort("\\B", b_sig);
+			first_cell->setPort("\\S", s_sig);
+            first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
+			first_cell->setPort("\\Y", last_cell->getPort("\\Y"));
+
+			cursor += cases;
+		}
+	}
+
+	void cleanup()
+	{
+		for (auto cell : remove_cells)
+			module->remove(cell);
+
+		remove_cells.clear();
+		sig_chain_next.clear();
+		sig_chain_prev.clear();
+		chain_start_cells.clear();
+	}
+
+	MuxpackWorker(Module *module) :
+			module(module), sigmap(module), mux_count(0), pmux_count(0)
+	{
+		make_sig_chain_next_prev();
+		find_chain_start_cells();
+
+		for (auto c : chain_start_cells) {
+			vector<Cell*> chain = create_chain(c);
+			process_chain(chain);
+		}
+
+		cleanup();
+	}
+};
+
+struct MuxpackPass : public Pass {
+	MuxpackPass() : Pass("muxpack", "TODO") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    muxpack [options] [selection]\n");
+		log("\n");
+        log("TODO");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing MUXPACK pass (TODO).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		int mux_count = 0;
+		int pmux_count = 0;
+
+		for (auto module : design->selected_modules()) {
+			MuxpackWorker worker(module);
+			mux_count += worker.mux_count;
+			pmux_count += worker.pmux_count;
+		}
+
+		log("Converted %d (p)mux cells into %d pmux cells.\n", mux_count, pmux_count);
+	}
+} MuxpackPass;
+
+PRIVATE_NAMESPACE_END

From 3e76e3a6fa4355e7223b10bba394f986d6821551 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 11:54:38 -0700
Subject: [PATCH 03/32] Add tests, fix for !=

---
 passes/techmap/muxpack.cc | 41 +++++++++++++++++++++++++++++---------
 tests/various/muxpack.v   | 36 +++++++++++++++++++++++++++++++++
 tests/various/muxpack.ys  | 42 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 110 insertions(+), 9 deletions(-)
 create mode 100644 tests/various/muxpack.v
 create mode 100644 tests/various/muxpack.ys

diff --git a/passes/techmap/muxpack.cc b/passes/techmap/muxpack.cc
index 4945affb0..54c52150a 100644
--- a/passes/techmap/muxpack.cc
+++ b/passes/techmap/muxpack.cc
@@ -54,14 +54,21 @@ struct MuxpackWorker
 			if (cell->type.in("$mux") && !cell->get_bool_attribute("\\keep"))
 			{
 				SigSpec a_sig = sigmap(cell->getPort("\\A"));
+				SigSpec b_sig = sigmap(cell->getPort("\\B"));
 				SigSpec y_sig = sigmap(cell->getPort("\\Y"));
    
 				if (sig_chain_next.count(a_sig))
                     for (auto a_bit : a_sig.bits())
                         sigbit_with_non_chain_users.insert(a_bit);
-                else
+				else
 					sig_chain_next[a_sig] = cell;
 
+				if (sig_chain_next.count(b_sig))
+					for (auto b_bit : b_sig.bits())
+						sigbit_with_non_chain_users.insert(b_bit);
+				else
+					sig_chain_next[b_sig] = cell;
+
 				sig_chain_prev[y_sig] = cell;
                 continue;
 			}
@@ -77,13 +84,22 @@ struct MuxpackWorker
 	{
 		for (auto it : sig_chain_next)
 		{
+			SigSpec next_sig;
+
             for (auto bit : it.first.bits())
                 if (sigbit_with_non_chain_users.count(bit))
                     goto start_cell;
 
-			if (sig_chain_prev.count(it.first) != 0)
+			next_sig = it.second->getPort("\\A");
+			if (sig_chain_prev.count(next_sig) == 0) {
+				next_sig = it.second->getPort("\\B");
+				if (sig_chain_prev.count(next_sig) == 0)
+					next_sig = SigSpec();
+			}
+
+			if (!next_sig.empty())
 			{
-				Cell *c1 = sig_chain_prev.at(it.first);
+				Cell *c1 = sig_chain_prev.at(next_sig);
 				Cell *c2 = it.second;
 
 				if (c1->type != c2->type)
@@ -149,15 +165,22 @@ struct MuxpackWorker
 			pmux_count += 1;
 
 			first_cell->type = "$pmux";
-            SigSpec b_sig = first_cell->getPort("\\B");
-            SigSpec s_sig = first_cell->getPort("\\S");
+			SigSpec b_sig = first_cell->getPort("\\B");
+			SigSpec s_sig = first_cell->getPort("\\S");
 
 			for (int i = 1; i < cases; i++) {
-                Cell* cursor_cell = chain[cursor+i];
-                b_sig.append(cursor_cell->getPort("\\B"));
-                s_sig.append(cursor_cell->getPort("\\S"));
+				Cell* prev_cell = chain[cursor+i-1];
+				Cell* cursor_cell = chain[cursor+i];
+				if (sigmap(prev_cell->getPort("\\Y")) == sigmap(cursor_cell->getPort("\\A"))) {
+					b_sig.append(cursor_cell->getPort("\\B"));
+					s_sig.append(cursor_cell->getPort("\\S"));
+				}
+				else {
+					b_sig.append(cursor_cell->getPort("\\A"));
+					s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort("\\S")));
+				}
 				remove_cells.insert(cursor_cell);
-            }
+			}
 
 			first_cell->setPort("\\B", b_sig);
 			first_cell->setPort("\\S", s_sig);
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
new file mode 100644
index 000000000..abc87ba44
--- /dev/null
+++ b/tests/various/muxpack.v
@@ -0,0 +1,36 @@
+module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s == 0) o <= i[0*W+:W];
+    else if (s == 1) o <= i[1*W+:W];
+    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+    else o <= {W{1'bx}};
+
+endmodule
+
+module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+end
+
+endmodule
+
+module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s != 0) 
+	   	if (s != 1) 
+			if (s != 2)
+				if (s != 3)
+					if (s != 4) o <= i[4*W+:W];
+					else o <= i[0*W+:W];
+				else o <= i[3*W+:W];
+			else o <= i[2*W+:W];
+		else o <= i[1*W+:W];
+    else o <= {W{1'bx}};
+
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
new file mode 100644
index 000000000..58c01cf05
--- /dev/null
+++ b/tests/various/muxpack.ys
@@ -0,0 +1,42 @@
+read_verilog muxpack.v
+design -save read
+hierarchy -top mux_if_unbal_4_1
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_invert
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter

From 5d4eca5a298d2f98de220cfd0efe5452ab4052d8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 11:59:41 -0700
Subject: [PATCH 04/32] Add a few more special case tests

---
 tests/various/muxpack.v  | 23 +++++++++++++++++++++++
 tests/various/muxpack.ys | 28 ++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index abc87ba44..333908fcb 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -34,3 +34,26 @@ always @*
     else o <= {W{1'bx}};
 
 endmodule
+
+module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o[W-2:0] <= i[2*W+:W-1];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+end
+
+endmodule
+
+module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    if (s == 0) o <= i[0*W+:W];
+//    else if (s == 1) o <= i[1*W+:W];
+//    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+    else o <= {W{1'bx}};
+end
+
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 58c01cf05..174eea74b 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -40,3 +40,31 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_width_mismatch
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 2 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_missing
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter

From b8620f7b3dde4460e5a8ed3ea7fd7aef54aa7da1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:03:44 -0700
Subject: [PATCH 05/32] One more and tidy up

---
 tests/various/muxpack.v  | 20 ++++++++++++++------
 tests/various/muxpack.ys | 16 +++++++++++++++-
 2 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 333908fcb..c2c2537a0 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -5,7 +5,6 @@ always @*
     else if (s == 2) o <= i[2*W+:W];
     else if (s == 3) o <= i[3*W+:W];
     else o <= {W{1'bx}};
-
 endmodule
 
 module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -17,7 +16,6 @@ always @* begin
     if (s == 3) o <= i[3*W+:W];
     if (s == 4) o <= i[4*W+:W];
 end
-
 endmodule
 
 module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -32,7 +30,6 @@ always @*
 			else o <= i[2*W+:W];
 		else o <= i[1*W+:W];
     else o <= {W{1'bx}};
-
 endmodule
 
 module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@@ -44,10 +41,9 @@ always @* begin
     if (s == 3) o <= i[3*W+:W];
     if (s == 4) o <= i[4*W+:W];
 end
-
 endmodule
 
-module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     if (s == 0) o <= i[0*W+:W];
 //    else if (s == 1) o <= i[1*W+:W];
@@ -55,5 +51,17 @@ always @* begin
     else if (s == 3) o <= i[3*W+:W];
     else o <= {W{1'bx}};
 end
-
 endmodule
+
+module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+    if (s == 0) o <= i[0*W+:W];
+end
+endmodule
+
+
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 174eea74b..a967ddfef 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -56,7 +56,21 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top mux_if_unbal_5_3_missing
+hierarchy -top mux_if_unbal_4_1_missing
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_order
 prep
 design -save gold
 muxpack

From 030f1d30e9cd04b4412114bdc93a15a39a4597c4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:04:42 -0700
Subject: [PATCH 06/32] Add to CHANGELOG

---
 CHANGELOG | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG b/CHANGELOG
index 36b64e111..e67d9c903 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
+    - Added "muxpack" pass
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 
 

From 3dd0682f298cec18f60c2d9da6417e287a385dd4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:11:59 -0700
Subject: [PATCH 07/32] Update doc

---
 passes/techmap/muxpack.cc | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/passes/techmap/muxpack.cc b/passes/techmap/muxpack.cc
index 54c52150a..9668b0d43 100644
--- a/passes/techmap/muxpack.cc
+++ b/passes/techmap/muxpack.cc
@@ -218,19 +218,20 @@ struct MuxpackWorker
 };
 
 struct MuxpackPass : public Pass {
-	MuxpackPass() : Pass("muxpack", "TODO") { }
+	MuxpackPass() : Pass("muxpack", "$mux cell cascades to $pmux") { }
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    muxpack [options] [selection]\n");
+		log("    muxpack [selection]\n");
 		log("\n");
-        log("TODO");
+		log("This pass converts cascaded chains of $mux cells (e.g. those created by if-else\n");
+		log("constructs) into $pmux cells.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-		log_header(design, "Executing MUXPACK pass (TODO).\n");
+		log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)

From 83450a94898321a239f67f92e05fb9a246f4dd6d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:15:13 -0700
Subject: [PATCH 08/32] Move muxpack from passes/techmap to passes/opt

---
 passes/opt/Makefile.inc            | 1 +
 passes/{techmap => opt}/muxpack.cc | 0
 passes/techmap/Makefile.inc        | 1 -
 3 files changed, 1 insertion(+), 1 deletion(-)
 rename passes/{techmap => opt}/muxpack.cc (100%)

diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc
index 337fee9e4..ea3646330 100644
--- a/passes/opt/Makefile.inc
+++ b/passes/opt/Makefile.inc
@@ -14,5 +14,6 @@ OBJS += passes/opt/opt_demorgan.o
 OBJS += passes/opt/rmports.o
 OBJS += passes/opt/opt_lut.o
 OBJS += passes/opt/pmux2shiftx.o
+OBJS += passes/opt/muxpack.o
 endif
 
diff --git a/passes/techmap/muxpack.cc b/passes/opt/muxpack.cc
similarity index 100%
rename from passes/techmap/muxpack.cc
rename to passes/opt/muxpack.cc
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 561636080..cf9e198ad 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -37,7 +37,6 @@ OBJS += passes/techmap/attrmap.o
 OBJS += passes/techmap/zinit.o
 OBJS += passes/techmap/dff2dffs.o
 OBJS += passes/techmap/flowmap.o
-OBJS += passes/techmap/muxpack.o
 endif
 
 GENFILES += passes/techmap/techmap.inc

From 705388eb24022d2a310ae72cd81e67a2f0ce7586 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:44:06 -0700
Subject: [PATCH 09/32] Add non exclusive test

---
 tests/various/muxpack.v  | 20 ++++++++++++++++++++
 tests/various/muxpack.ys | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index c2c2537a0..e847fef27 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -64,4 +64,24 @@ always @* begin
 end
 endmodule
 
+module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s == 0) o <= i[0*W+:W];
+    else if (s == 1) o <= i[1*W+:W];
+    else if (s == 2) o <= i[2*W+:W];
+    else if (s == 3) o <= i[3*W+:W];
+	else if (s == 0) o <= {W{1'b0}};
+    else o <= {W{1'bx}};
+endmodule
 
+module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    if (s == 0) o <= i[0*W+:W];
+    if (s == 1) o <= i[1*W+:W];
+    if (s == 2) o <= i[2*W+:W];
+    if (s == 3) o <= i[3*W+:W];
+    if (s == 4) o <= i[4*W+:W];
+	if (s == 0) o <= i[2*W+:W];
+end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index a967ddfef..178860b88 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -6,6 +6,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -20,6 +21,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -34,6 +36,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -48,6 +51,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 2 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -62,6 +66,7 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold
@@ -76,6 +81,37 @@ design -save gold
 muxpack
 opt
 stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_4_1_nonexcl
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_unbal_5_3_nonexcl
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
 select -assert-count 1 t:$pmux
 design -stash gate
 design -import gold -as gold

From d2172c6846f710e9a362708e3308dd302110deb2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:44:50 -0700
Subject: [PATCH 10/32] Non chain user check using next_sig

---
 passes/opt/muxpack.cc | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 9668b0d43..963083107 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -84,19 +84,17 @@ struct MuxpackWorker
 	{
 		for (auto it : sig_chain_next)
 		{
-			SigSpec next_sig;
-
-            for (auto bit : it.first.bits())
-                if (sigbit_with_non_chain_users.count(bit))
-                    goto start_cell;
-
-			next_sig = it.second->getPort("\\A");
+			SigSpec next_sig = it.second->getPort("\\A");
 			if (sig_chain_prev.count(next_sig) == 0) {
 				next_sig = it.second->getPort("\\B");
 				if (sig_chain_prev.count(next_sig) == 0)
 					next_sig = SigSpec();
 			}
 
+			for (auto bit : next_sig.bits())
+				if (sigbit_with_non_chain_users.count(bit))
+					goto start_cell;
+
 			if (!next_sig.empty())
 			{
 				Cell *c1 = sig_chain_prev.at(next_sig);

From 978fda94f684185a7d583a3865b7a68459344e46 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:46:42 -0700
Subject: [PATCH 11/32] Fix spacing

---
 passes/opt/muxpack.cc | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 963083107..cb13a45b0 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -43,9 +43,8 @@ struct MuxpackWorker
 		for (auto wire : module->wires())
 		{
 			if (wire->port_output || wire->get_bool_attribute("\\keep")) {
-				for (auto bit : sigmap(wire)) {
+				for (auto bit : sigmap(wire))
 					sigbit_with_non_chain_users.insert(bit);
-                }
 			}
 		}
 
@@ -58,8 +57,8 @@ struct MuxpackWorker
 				SigSpec y_sig = sigmap(cell->getPort("\\Y"));
    
 				if (sig_chain_next.count(a_sig))
-                    for (auto a_bit : a_sig.bits())
-                        sigbit_with_non_chain_users.insert(a_bit);
+					for (auto a_bit : a_sig.bits())
+						sigbit_with_non_chain_users.insert(a_bit);
 				else
 					sig_chain_next[a_sig] = cell;
 
@@ -70,7 +69,7 @@ struct MuxpackWorker
 					sig_chain_next[b_sig] = cell;
 
 				sig_chain_prev[y_sig] = cell;
-                continue;
+				continue;
 			}
 
 			for (auto conn : cell->connections())
@@ -182,7 +181,7 @@ struct MuxpackWorker
 
 			first_cell->setPort("\\B", b_sig);
 			first_cell->setPort("\\S", s_sig);
-            first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
+			first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
 			first_cell->setPort("\\Y", last_cell->getPort("\\Y"));
 
 			cursor += cases;

From dc7b8c4b942f9d9bc61a87a81291244d0b73843b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 12:56:34 -0700
Subject: [PATCH 12/32] More cleanup

---
 passes/opt/muxpack.cc | 35 ++++++++++++++++++++---------------
 1 file changed, 20 insertions(+), 15 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index cb13a45b0..ae4b67db2 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -37,6 +37,7 @@ struct MuxpackWorker
 	dict<SigSpec, Cell*> sig_chain_prev;
 	pool<SigBit> sigbit_with_non_chain_users;
 	pool<Cell*> chain_start_cells;
+	pool<Cell*> candidate_cells;
 
 	void make_sig_chain_next_prev()
 	{
@@ -59,14 +60,18 @@ struct MuxpackWorker
 				if (sig_chain_next.count(a_sig))
 					for (auto a_bit : a_sig.bits())
 						sigbit_with_non_chain_users.insert(a_bit);
-				else
+				else {
 					sig_chain_next[a_sig] = cell;
+					candidate_cells.insert(cell);
+				}
 
 				if (sig_chain_next.count(b_sig))
 					for (auto b_bit : b_sig.bits())
 						sigbit_with_non_chain_users.insert(b_bit);
-				else
+				else {
 					sig_chain_next[b_sig] = cell;
+					candidate_cells.insert(cell);
+				}
 
 				sig_chain_prev[y_sig] = cell;
 				continue;
@@ -81,35 +86,34 @@ struct MuxpackWorker
 
 	void find_chain_start_cells()
 	{
-		for (auto it : sig_chain_next)
+		for (auto cell : candidate_cells)
 		{
-			SigSpec next_sig = it.second->getPort("\\A");
+			SigSpec next_sig = cell->getPort("\\A");
 			if (sig_chain_prev.count(next_sig) == 0) {
-				next_sig = it.second->getPort("\\B");
+				next_sig = cell->getPort("\\B");
 				if (sig_chain_prev.count(next_sig) == 0)
-					next_sig = SigSpec();
+					goto start_cell;
 			}
 
-			for (auto bit : next_sig.bits())
-				if (sigbit_with_non_chain_users.count(bit))
-					goto start_cell;
-
-			if (!next_sig.empty())
 			{
+				for (auto bit : next_sig.bits())
+					if (sigbit_with_non_chain_users.count(bit))
+						goto start_cell;
+
 				Cell *c1 = sig_chain_prev.at(next_sig);
-				Cell *c2 = it.second;
+				Cell *c2 = cell;
 
 				if (c1->type != c2->type)
 					goto start_cell;
 
 				if (c1->parameters != c2->parameters)
 					goto start_cell;
-
-				continue;
 			}
 
+			continue;
+
 		start_cell:
-			chain_start_cells.insert(it.second);
+			chain_start_cells.insert(cell);
 		}
 	}
 
@@ -197,6 +201,7 @@ struct MuxpackWorker
 		sig_chain_next.clear();
 		sig_chain_prev.clear();
 		chain_start_cells.clear();
+		candidate_cells.clear();
 	}
 
 	MuxpackWorker(Module *module) :

From ccdf989025e57da7dfd5ab609676ebe3cfb2c2d6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 13:51:22 -0700
Subject: [PATCH 13/32] Support cascading $pmux.A with $mux.A and $mux.B

---
 passes/opt/muxpack.cc    | 42 ++++++++++++++++++++++++----------------
 tests/various/muxpack.v  | 25 ++++++++++++++++++++++++
 tests/various/muxpack.ys | 15 ++++++++++++++
 3 files changed, 65 insertions(+), 17 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index ae4b67db2..f9e5c8f09 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -51,10 +51,12 @@ struct MuxpackWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in("$mux") && !cell->get_bool_attribute("\\keep"))
+			if (cell->type.in("$mux", "$pmux") && !cell->get_bool_attribute("\\keep"))
 			{
 				SigSpec a_sig = sigmap(cell->getPort("\\A"));
-				SigSpec b_sig = sigmap(cell->getPort("\\B"));
+				SigSpec b_sig;
+				if (cell->type == "$mux")
+					b_sig = sigmap(cell->getPort("\\B"));
 				SigSpec y_sig = sigmap(cell->getPort("\\Y"));
    
 				if (sig_chain_next.count(a_sig))
@@ -65,12 +67,14 @@ struct MuxpackWorker
 					candidate_cells.insert(cell);
 				}
 
-				if (sig_chain_next.count(b_sig))
-					for (auto b_bit : b_sig.bits())
-						sigbit_with_non_chain_users.insert(b_bit);
-				else {
-					sig_chain_next[b_sig] = cell;
-					candidate_cells.insert(cell);
+				if (!b_sig.empty()) {
+					if (sig_chain_next.count(b_sig))
+						for (auto b_bit : b_sig.bits())
+							sigbit_with_non_chain_users.insert(b_bit);
+					else {
+						sig_chain_next[b_sig] = cell;
+						candidate_cells.insert(cell);
+					}
 				}
 
 				sig_chain_prev[y_sig] = cell;
@@ -88,10 +92,16 @@ struct MuxpackWorker
 	{
 		for (auto cell : candidate_cells)
 		{
+			log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
+
 			SigSpec next_sig = cell->getPort("\\A");
 			if (sig_chain_prev.count(next_sig) == 0) {
-				next_sig = cell->getPort("\\B");
-				if (sig_chain_prev.count(next_sig) == 0)
+				if (cell->type == "$mux") {
+					next_sig = cell->getPort("\\B");
+					if (sig_chain_prev.count(next_sig) == 0)
+						goto start_cell;
+				}
+				else
 					goto start_cell;
 			}
 
@@ -103,10 +113,7 @@ struct MuxpackWorker
 				Cell *c1 = sig_chain_prev.at(next_sig);
 				Cell *c2 = cell;
 
-				if (c1->type != c2->type)
-					goto start_cell;
-
-				if (c1->parameters != c2->parameters)
+				if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH"))
 					goto start_cell;
 			}
 
@@ -220,15 +227,16 @@ struct MuxpackWorker
 };
 
 struct MuxpackPass : public Pass {
-	MuxpackPass() : Pass("muxpack", "$mux cell cascades to $pmux") { }
+	MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { }
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    muxpack [selection]\n");
 		log("\n");
-		log("This pass converts cascaded chains of $mux cells (e.g. those created by if-else\n");
-		log("constructs) into $pmux cells.\n");
+		log("This pass converts cascaded chains of $pmux cells (e.g. those create from case\n");
+		log("constructs) and $mux cells (e.g. those created by if-else constructs) into \n");
+		log("into $pmux cells.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index e847fef27..fe0150532 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -85,3 +85,28 @@ always @* begin
 	if (s == 0) o <= i[2*W+:W];
 end
 endmodule
+
+module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {W{1'bx}};
+    case (s)
+    0: o <= i[0*W+:W];
+    default:
+        case (s)
+        1: o <= i[1*W+:W];
+        2: o <= i[2*W+:W];
+        default:
+            case (s)
+            3: o <= i[3*W+:W];
+            4: o <= i[4*W+:W];
+            5: o <= i[5*W+:W];
+            default:
+                case (s)
+                    6: o <= i[6*W+:W];
+                    default: o <= i[7*W+:W];
+                endcase
+            endcase
+        endcase
+    endcase
+end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 178860b88..4dcb9ed89 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -118,3 +118,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_case_unbal_7_7
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter

From 0a66720f6f67b087fe6342d01d45944506240942 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 14:01:42 -0700
Subject: [PATCH 14/32] Fix warnings

---
 tests/various/muxpack.v  | 4 ++--
 tests/various/muxpack.ys | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index fe0150532..7c189fff8 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -74,7 +74,7 @@ always @*
     else o <= {W{1'bx}};
 endmodule
 
-module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     o <= {W{1'bx}};
     if (s == 0) o <= i[0*W+:W];
@@ -86,7 +86,7 @@ always @* begin
 end
 endmodule
 
-module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     o <= {W{1'bx}};
     case (s)
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 4dcb9ed89..0c5b82818 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top mux_case_unbal_7_7
+hierarchy -top mux_case_unbal_8_7
 prep
 design -save gold
 muxpack

From 5c277c6325b78bfe18cf294b63ea69ff272e69c5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 14:21:34 -0700
Subject: [PATCH 15/32] Fix and test for balanced case

---
 passes/opt/muxpack.cc    | 24 ++++++++++++++----------
 tests/various/muxpack.v  | 26 ++++++++++++++++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 3 files changed, 55 insertions(+), 10 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index f9e5c8f09..8c4db4e4d 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -94,23 +94,27 @@ struct MuxpackWorker
 		{
 			log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
 
-			SigSpec next_sig = cell->getPort("\\A");
-			if (sig_chain_prev.count(next_sig) == 0) {
-				if (cell->type == "$mux") {
-					next_sig = cell->getPort("\\B");
-					if (sig_chain_prev.count(next_sig) == 0)
-						goto start_cell;
-				}
-				else
+			SigSpec a_sig = cell->getPort("\\A");
+			if (cell->type == "$mux") {
+				SigSpec b_sig = cell->getPort("\\B");
+				if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
+					goto start_cell;
+
+				if (!sig_chain_prev.count(a_sig))
+					a_sig = b_sig;
+			}
+			else if (cell->type == "$pmux") {
+				if (!sig_chain_prev.count(a_sig))
 					goto start_cell;
 			}
+			else log_abort();
 
 			{
-				for (auto bit : next_sig.bits())
+				for (auto bit : a_sig.bits())
 					if (sigbit_with_non_chain_users.count(bit))
 						goto start_cell;
 
-				Cell *c1 = sig_chain_prev.at(next_sig);
+				Cell *c1 = sig_chain_prev.at(a_sig);
 				Cell *c2 = cell;
 
 				if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH"))
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 7c189fff8..f1bd5ea8e 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -110,3 +110,29 @@ always @* begin
     endcase
 end
 endmodule
+
+module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[0*W+:W];
+      else
+       o <= i[1*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[2*W+:W];
+      else
+       o <= i[3*W+:W];
+    else
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[4*W+:W];
+      else
+       o <= i[5*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[6*W+:W];
+      else
+       o <= i[7*W+:W];
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 0c5b82818..9ea743b9f 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -133,3 +133,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_bal_8_2
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 7 t:$mux
+select -assert-count 0 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter

From 0f6e914ef63d06ae77b54d246b61118c19647f26 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 08:34:58 -0700
Subject: [PATCH 16/32] Another muxpack test

---
 tests/various/muxpack.v  | 17 +++++++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index f1bd5ea8e..41dfed396 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -136,3 +136,20 @@ always @*
       else
        o <= i[7*W+:W];
 endmodule
+
+module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @*
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      if (s[2] == 1'b0)
+       o <= i[0*W+:W];
+      else
+       o <= i[1*W+:W];
+     else
+      if (s[2] == 1'b0)
+       o <= i[2*W+:W];
+      else
+       o <= i[3*W+:W];
+    else
+     o <= i[4*W+:W];
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 9ea743b9f..dd3c143d8 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -148,3 +148,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top mux_if_bal_5_1
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 2 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter

From 5ab59cd59ee90abc4b6991486854dbe4c3f4d0a4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 11:36:19 -0700
Subject: [PATCH 17/32] Resolve @cliffordwolf comment on sigmap

---
 passes/opt/muxpack.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 8c4db4e4d..b060389e3 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -94,9 +94,9 @@ struct MuxpackWorker
 		{
 			log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
 
-			SigSpec a_sig = cell->getPort("\\A");
+			SigSpec a_sig = sigmap(cell->getPort("\\A"));
 			if (cell->type == "$mux") {
-				SigSpec b_sig = cell->getPort("\\B");
+				SigSpec b_sig = sigmap(cell->getPort("\\B"));
 				if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
 					goto start_cell;
 

From 887df8914c64220b9f306b7d21f199fa247224fd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 11:37:52 -0700
Subject: [PATCH 18/32] Resolve @cliffordwolf comment on redundant check

---
 passes/opt/muxpack.cc | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index b060389e3..15a646e2e 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -109,17 +109,9 @@ struct MuxpackWorker
 			}
 			else log_abort();
 
-			{
-				for (auto bit : a_sig.bits())
-					if (sigbit_with_non_chain_users.count(bit))
-						goto start_cell;
-
-				Cell *c1 = sig_chain_prev.at(a_sig);
-				Cell *c2 = cell;
-
-				if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH"))
+			for (auto bit : a_sig.bits())
+				if (sigbit_with_non_chain_users.count(bit))
 					goto start_cell;
-			}
 
 			continue;
 

From e263bc249b905195120fbc074c6f80d03fb21cf8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 11:54:29 -0700
Subject: [PATCH 19/32] Add nonexclusive test from @cliffordwolf

---
 tests/various/muxpack.v  | 13 +++++++++++++
 tests/various/muxpack.ys | 15 +++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 41dfed396..f3c25db8d 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -153,3 +153,16 @@ always @*
     else
      o <= i[4*W+:W];
 endmodule
+
+module cliffordwolf_nonexclusive_select (
+        input wire x, y, z,
+        input wire a, b, c, d,
+        output reg o
+);
+        always @* begin
+                o = a;
+                if (x) o = b;
+                if (y) o = c;
+                if (z) o = d;
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index dd3c143d8..7c3fe5070 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -163,3 +163,18 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top cliffordwolf_nonexclusive_select
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter

From 1da12c5071a738504d22e68d66cab7c5c5afb07e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 12:12:11 -0700
Subject: [PATCH 20/32] Add @cliffordwolf freduce testcase

---
 tests/various/muxpack.v  | 13 +++++++++++++
 tests/various/muxpack.ys | 17 +++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index f3c25db8d..d45ce4045 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -166,3 +166,16 @@ module cliffordwolf_nonexclusive_select (
                 if (z) o = d;
         end
 endmodule
+
+module cliffordwolf_freduce (
+        input wire [1:0] s,
+        input wire a, b, c, d,
+        output reg [3:0] o
+);
+        always @* begin
+                o = {4{a}};
+                if (s == 0) o = {3{b}};
+                if (s == 1) o = {2{c}};
+                if (s == 2) o = d;
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 7c3fe5070..afdacdf30 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -178,3 +178,20 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top cliffordwolf_freduce
+prep
+design -save gold
+proc; opt; freduce; opt
+write_verilog -noexpr -norename
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter

From 9b408838f191bb0390b6edff55770cab8e8ca15d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 14:18:17 -0700
Subject: [PATCH 21/32] Add ExclusiveDatabase to check exclusive $eq/$logic_not
 cell results

---
 passes/opt/muxpack.cc | 65 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 15a646e2e..0cf9e0e30 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -24,6 +24,58 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+struct ExclusiveDatabase
+{
+	Module *module;
+	const SigMap &sigmap;
+
+	dict<SigSpec, SigSpec> sig_cmp_prev;
+	dict<SigSpec, pool<SigSpec>> sig_exclusive;
+
+	ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
+	{
+		SigSpec a_port, b_port, y_port;
+		for (auto cell : module->cells()) {
+			if (cell->type == "$eq") {
+				a_port = sigmap(cell->getPort("\\A"));
+				b_port = sigmap(cell->getPort("\\B"));
+				if (!b_port.is_fully_const()) {
+					if (!a_port.is_fully_const())
+						continue;
+					std::swap(a_port, b_port);
+				}
+				y_port = sigmap(cell->getPort("\\Y"));
+			}
+			else if (cell->type == "$logic_not") {
+				a_port = sigmap(cell->getPort("\\A"));
+				b_port = Const(RTLIL::S0, GetSize(a_port));
+				y_port = sigmap(cell->getPort("\\Y"));
+			}
+			else continue;
+
+			auto r = sig_exclusive[a_port].insert(b_port.as_const());
+			if (!r.second)
+				continue;
+			sig_cmp_prev[y_port] = a_port;
+		}
+	}
+
+	bool query(const SigSpec& sig1, const SigSpec& sig2) const
+	{
+		auto it = sig_cmp_prev.find(sig1);
+		if (it == sig_cmp_prev.end())
+			return false;
+
+		auto jt = sig_cmp_prev.find(sig2);
+		if (jt == sig_cmp_prev.end())
+			return false;
+
+		log("query = %s %s\n", log_signal(it->second), log_signal(jt->second));
+		return it->second == jt->second;
+	}
+};
+
+
 struct MuxpackWorker
 {
 	Module *module;
@@ -39,6 +91,8 @@ struct MuxpackWorker
 	pool<Cell*> chain_start_cells;
 	pool<Cell*> candidate_cells;
 
+	ExclusiveDatabase excl_db;
+
 	void make_sig_chain_next_prev()
 	{
 		for (auto wire : module->wires())
@@ -90,6 +144,7 @@ struct MuxpackWorker
 
 	void find_chain_start_cells()
 	{
+		Cell* first_cell = nullptr;
 		for (auto cell : candidate_cells)
 		{
 			log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
@@ -102,6 +157,13 @@ struct MuxpackWorker
 
 				if (!sig_chain_prev.count(a_sig))
 					a_sig = b_sig;
+
+				if (first_cell) {
+					SigSpec s_sig = sigmap(cell->getPort("\\S"));
+					SigSpec prev_s_sig = sigmap(first_cell->getPort("\\S"));
+					if (!excl_db.query(prev_s_sig, s_sig))
+						goto start_cell;
+				}
 			}
 			else if (cell->type == "$pmux") {
 				if (!sig_chain_prev.count(a_sig))
@@ -117,6 +179,7 @@ struct MuxpackWorker
 
 		start_cell:
 			chain_start_cells.insert(cell);
+			first_cell = cell;
 		}
 	}
 
@@ -208,7 +271,7 @@ struct MuxpackWorker
 	}
 
 	MuxpackWorker(Module *module) :
-			module(module), sigmap(module), mux_count(0), pmux_count(0)
+			module(module), sigmap(module), mux_count(0), pmux_count(0), excl_db(module, sigmap)
 	{
 		make_sig_chain_next_prev();
 		find_chain_start_cells();

From ba52d9b4716b287b0a469597b748f9859e897329 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 15:34:16 -0700
Subject: [PATCH 22/32] Extend ExclusiveDatabase to query SigSpec-s (for $pmux)

---
 passes/opt/muxpack.cc | 44 +++++++++++++++++++++++++------------------
 1 file changed, 26 insertions(+), 18 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 0cf9e0e30..4b02df394 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -29,7 +29,7 @@ struct ExclusiveDatabase
 	Module *module;
 	const SigMap &sigmap;
 
-	dict<SigSpec, SigSpec> sig_cmp_prev;
+	dict<SigBit, SigSpec> sig_cmp_prev;
 	dict<SigSpec, pool<SigSpec>> sig_exclusive;
 
 	ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
@@ -62,16 +62,23 @@ struct ExclusiveDatabase
 
 	bool query(const SigSpec& sig1, const SigSpec& sig2) const
 	{
-		auto it = sig_cmp_prev.find(sig1);
-		if (it == sig_cmp_prev.end())
-			return false;
+		// FIXME: O(N)
+		for (auto bit1 : sig1.bits()) {
+			auto it = sig_cmp_prev.find(bit1);
+			if (it == sig_cmp_prev.end())
+				return false;
 
-		auto jt = sig_cmp_prev.find(sig2);
-		if (jt == sig_cmp_prev.end())
-			return false;
+			for (auto bit2 : sig2.bits()) {
+				auto jt = sig_cmp_prev.find(bit2);
+				if (jt == sig_cmp_prev.end())
+					return false;
 
-		log("query = %s %s\n", log_signal(it->second), log_signal(jt->second));
-		return it->second == jt->second;
+				if (it->second != jt->second)
+					return false;
+			}
+		}
+
+		return true;
 	}
 };
 
@@ -144,7 +151,6 @@ struct MuxpackWorker
 
 	void find_chain_start_cells()
 	{
-		Cell* first_cell = nullptr;
 		for (auto cell : candidate_cells)
 		{
 			log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
@@ -157,13 +163,6 @@ struct MuxpackWorker
 
 				if (!sig_chain_prev.count(a_sig))
 					a_sig = b_sig;
-
-				if (first_cell) {
-					SigSpec s_sig = sigmap(cell->getPort("\\S"));
-					SigSpec prev_s_sig = sigmap(first_cell->getPort("\\S"));
-					if (!excl_db.query(prev_s_sig, s_sig))
-						goto start_cell;
-				}
 			}
 			else if (cell->type == "$pmux") {
 				if (!sig_chain_prev.count(a_sig))
@@ -175,11 +174,19 @@ struct MuxpackWorker
 				if (sigbit_with_non_chain_users.count(bit))
 					goto start_cell;
 
+			{
+				Cell *prev_cell = sig_chain_prev.at(a_sig);
+				log_assert(prev_cell);
+				SigSpec s_sig = sigmap(cell->getPort("\\S"));
+				SigSpec next_s_sig = sigmap(prev_cell->getPort("\\S"));
+				if (!excl_db.query(s_sig, next_s_sig))
+					goto start_cell;
+			}
+
 			continue;
 
 		start_cell:
 			chain_start_cells.insert(cell);
-			first_cell = cell;
 		}
 	}
 
@@ -243,6 +250,7 @@ struct MuxpackWorker
 					s_sig.append(cursor_cell->getPort("\\S"));
 				}
 				else {
+					log_assert(cursor_cell->type == "$mux");
 					b_sig.append(cursor_cell->getPort("\\A"));
 					s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort("\\S")));
 				}

From b959bf79c004fdf81ccc397d5aa774b67a09d6da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 15:35:15 -0700
Subject: [PATCH 23/32] Add nonexcl case test, comment out two others

---
 tests/various/muxpack.v  | 18 ++++++++++++
 tests/various/muxpack.ys | 61 +++++++++++++++++++++++++---------------
 2 files changed, 57 insertions(+), 22 deletions(-)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index d45ce4045..3a1086dbf 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -179,3 +179,21 @@ module cliffordwolf_freduce (
                 if (s == 2) o = d;
         end
 endmodule
+
+module case_nonexclusive_select (
+        input wire [1:0] x, y,
+        input wire a, b, c, d, e,
+        output reg o
+);
+        always @* begin
+            case (x)
+                0, 2: o = b;
+                1: o = c;
+                default: begin
+                    o = a;
+                    if (y == 0) o = d;
+                    if (y == 1) o = e;
+                end
+        endcase
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index afdacdf30..579dad8d3 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -1,5 +1,6 @@
 read_verilog muxpack.v
 design -save read
+
 hierarchy -top mux_if_unbal_4_1
 prep
 design -save gold
@@ -29,20 +30,21 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
-design -load read
-hierarchy -top mux_if_unbal_5_3_invert
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
+# TODO: Currently ExclusiveDatabase only analyses $eq cells
+#design -load read
+#hierarchy -top mux_if_unbal_5_3_invert
+#prep
+#design -save gold
+#muxpack
+#opt
+#stat
+#select -assert-count 0 t:$mux
+#select -assert-count 1 t:$pmux
+#design -stash gate
+#design -import gold -as gold
+#design -import gate -as gate
+#miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -show-ports miter
 
 design -load read
 hierarchy -top mux_if_unbal_5_3_width_mismatch
@@ -156,8 +158,8 @@ design -save gold
 muxpack
 opt
 stat
-select -assert-count 2 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 4 t:$mux
+select -assert-count 0 t:$pmux
 design -stash gate
 design -import gold -as gold
 design -import gate -as gate
@@ -171,25 +173,40 @@ design -save gold
 muxpack
 opt
 stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 3 t:$mux
+select -assert-count 0 t:$pmux
 design -stash gate
 design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
+#design -load read
+#hierarchy -top cliffordwolf_freduce
+#prep
+#design -save gold
+#proc; opt; freduce; opt
+#show
+#muxpack
+#opt
+#stat
+#select -assert-count 0 t:$mux
+#select -assert-count 1 t:$pmux
+#design -stash gate
+#design -import gold -as gold
+#design -import gate -as gate
+#miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -show-ports miter
+
 design -load read
-hierarchy -top cliffordwolf_freduce
+hierarchy -top case_nonexclusive_select
 prep
 design -save gold
-proc; opt; freduce; opt
-write_verilog -noexpr -norename
 muxpack
 opt
 stat
 select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 2 t:$pmux
 design -stash gate
 design -import gold -as gold
 design -import gate -as gate

From f705f6a0b5d19d38cf41ba5f782847de54110463 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 15:39:12 -0700
Subject: [PATCH 24/32] Comment O(N) -> O(N^2)

---
 passes/opt/muxpack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 4b02df394..f01d5474d 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -62,7 +62,7 @@ struct ExclusiveDatabase
 
 	bool query(const SigSpec& sig1, const SigSpec& sig2) const
 	{
-		// FIXME: O(N)
+		// FIXME: O(N^2)
 		for (auto bit1 : sig1.bits()) {
 			auto it = sig_cmp_prev.find(bit1);
 			if (it == sig_cmp_prev.end())

From 5b999ae68decef5646ef0ccac53463f22fe18d8f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 10:32:19 -0700
Subject: [PATCH 25/32] Elaborate muxpack doc

---
 passes/opt/muxpack.cc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index f01d5474d..b6f3313bf 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -302,8 +302,12 @@ struct MuxpackPass : public Pass {
 		log("    muxpack [selection]\n");
 		log("\n");
 		log("This pass converts cascaded chains of $pmux cells (e.g. those create from case\n");
-		log("constructs) and $mux cells (e.g. those created by if-else constructs) into \n");
-		log("into $pmux cells.\n");
+		log("constructs) and $mux cells (e.g. those created by if-else constructs) into\n");
+		log("$pmux cells.\n");
+		log("\n");
+		log("This optimisation is conservative --- it will only pack $mux or $pmux cells with\n");
+		log("other such cells if it can be certain that the select lines are mutually\n");
+		log("exclusive.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE

From 641b86d25f5baa898bf5fca3d1a8f2fd4f5954e6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 11:45:31 -0700
Subject: [PATCH 26/32] Fix up ExclusiveDatabase with @cliffordwolf's help

---
 passes/opt/muxpack.cc | 65 +++++++++++++++++++++----------------------
 1 file changed, 32 insertions(+), 33 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index b6f3313bf..ae4f7ba9c 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -29,54 +29,53 @@ struct ExclusiveDatabase
 	Module *module;
 	const SigMap &sigmap;
 
-	dict<SigBit, SigSpec> sig_cmp_prev;
-	dict<SigSpec, pool<SigSpec>> sig_exclusive;
+	dict<SigBit, std::pair<SigSpec,Const>> sig_cmp_prev;
 
 	ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
 	{
-		SigSpec a_port, b_port, y_port;
+		SigSpec const_sig, nonconst_sig, y_port;
 		for (auto cell : module->cells()) {
 			if (cell->type == "$eq") {
-				a_port = sigmap(cell->getPort("\\A"));
-				b_port = sigmap(cell->getPort("\\B"));
-				if (!b_port.is_fully_const()) {
-					if (!a_port.is_fully_const())
+				nonconst_sig = sigmap(cell->getPort("\\A"));
+				const_sig = sigmap(cell->getPort("\\B"));
+				if (!const_sig.is_fully_const()) {
+					if (!nonconst_sig.is_fully_const())
 						continue;
-					std::swap(a_port, b_port);
+					std::swap(nonconst_sig, const_sig);
 				}
 				y_port = sigmap(cell->getPort("\\Y"));
 			}
 			else if (cell->type == "$logic_not") {
-				a_port = sigmap(cell->getPort("\\A"));
-				b_port = Const(RTLIL::S0, GetSize(a_port));
+				nonconst_sig = sigmap(cell->getPort("\\A"));
+				const_sig = Const(RTLIL::S0, GetSize(nonconst_sig));
 				y_port = sigmap(cell->getPort("\\Y"));
 			}
 			else continue;
 
-			auto r = sig_exclusive[a_port].insert(b_port.as_const());
-			if (!r.second)
-				continue;
-			sig_cmp_prev[y_port] = a_port;
-		}
-	}
+                        log_assert(!nonconst_sig.empty());
+                        log_assert(!const_sig.empty());
+                        sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,const_sig.as_const());
+                }
+        }
 
-	bool query(const SigSpec& sig1, const SigSpec& sig2) const
-	{
-		// FIXME: O(N^2)
-		for (auto bit1 : sig1.bits()) {
-			auto it = sig_cmp_prev.find(bit1);
-			if (it == sig_cmp_prev.end())
-				return false;
+        bool query(const SigSpec &sig) const
+        {
+                SigSpec nonconst_sig;
+                pool<Const> const_values;
 
-			for (auto bit2 : sig2.bits()) {
-				auto jt = sig_cmp_prev.find(bit2);
-				if (jt == sig_cmp_prev.end())
-					return false;
+                for (auto bit : sig.bits()) {
+                        auto it = sig_cmp_prev.find(bit);
+                        if (it == sig_cmp_prev.end())
+                                return false;
 
-				if (it->second != jt->second)
-					return false;
-			}
-		}
+                        if (nonconst_sig.empty())
+                                nonconst_sig = it->second.first;
+                        else if (nonconst_sig != it->second.first)
+                                return false;
+
+                        if (!const_values.insert(it->second.second).second)
+                                return false;
+                }
 
 		return true;
 	}
@@ -178,8 +177,8 @@ struct MuxpackWorker
 				Cell *prev_cell = sig_chain_prev.at(a_sig);
 				log_assert(prev_cell);
 				SigSpec s_sig = sigmap(cell->getPort("\\S"));
-				SigSpec next_s_sig = sigmap(prev_cell->getPort("\\S"));
-				if (!excl_db.query(s_sig, next_s_sig))
+				s_sig.append(sigmap(prev_cell->getPort("\\S")));
+				if (!excl_db.query(s_sig))
 					goto start_cell;
 			}
 

From 6ec816098153c733b97410ebc6aef166db8affd8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 11:45:53 -0700
Subject: [PATCH 27/32] Add more muxpack tests, with overlapping entries

---
 tests/various/muxpack.v  | 55 +++++++++++++++++++++++++++++++++++++++-
 tests/various/muxpack.ys | 30 ++++++++++++++++++++++
 2 files changed, 84 insertions(+), 1 deletion(-)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 3a1086dbf..7a658d754 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -187,7 +187,9 @@ module case_nonexclusive_select (
 );
         always @* begin
             case (x)
-                0, 2: o = b;
+                //0, 2: o = b;
+                0: o = b;
+                2: o = b;
                 1: o = c;
                 default: begin
                     o = a;
@@ -197,3 +199,54 @@ module case_nonexclusive_select (
         endcase
         end
 endmodule
+
+module case_nonoverlap (
+        input wire [2:0] x,
+        input wire a, b, c, d, e, f, g,
+        output reg o
+);
+        always @* begin
+            case (x)
+                //0, 2: o = b; // Creates $reduce_or
+                //0: o = b; 2: o = b; // Creates $reduce_or
+                0: o = b;
+                2: o = f;
+                1: o = c;
+                default:
+                    case (x)
+                        //3, 4: o = d; // Creates $reduce_or
+                        //3: o = d; 4: o = d; // Creates $reduce_or
+                        3: o = d;
+                        4: o = g;
+                        5: o = e;
+                        default: o = 1'b0;
+                    endcase
+        endcase
+        end
+endmodule
+
+module case_overlap (
+        input wire [2:0] x,
+        input wire a, b, c, d, e, f, g,
+        output reg o
+);
+        always @* begin
+            case (x)
+                //0, 2: o = b; // Creates $reduce_or
+                //0: o = b; 2: o = b; // Creates $reduce_or
+                0: o = b;
+                2: o = f;
+                1: o = c;
+                default:
+                    case (x)
+                        //3, 4: o = d; // Creates $reduce_or
+                        //3: o = d; 4: o = d; // Creates $reduce_or
+                        2: o = 1'b1; // Overlaps with previous $pmux
+                        3: o = d;
+                        4: o = g;
+                        5: o = e;
+                        default: o = 1'b0;
+                    endcase
+        endcase
+        end
+endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 579dad8d3..ef8a6dab9 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -212,3 +212,33 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_nonoverlap
+prep
+design -save gold
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_overlap
+prep
+design -save gold
+muxpack
+#opt # Do not opt otherwise $pmux's overlapping entry will get removed
+stat
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter

From d89d663c92853fcd7f9d75b392ec4133ba2f1d89 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 11:52:28 -0700
Subject: [PATCH 28/32] Add doc

---
 passes/opt/muxpack.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index ae4f7ba9c..c8b226c78 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -304,9 +304,9 @@ struct MuxpackPass : public Pass {
 		log("constructs) and $mux cells (e.g. those created by if-else constructs) into\n");
 		log("$pmux cells.\n");
 		log("\n");
-		log("This optimisation is conservative --- it will only pack $mux or $pmux cells with\n");
-		log("other such cells if it can be certain that the select lines are mutually\n");
-		log("exclusive.\n");
+		log("This optimisation is conservative --- it will only pack $mux or $pmux cells\n");
+		log("whose select lines are driven by '$eq' cells with other such cells if it can be\n");
+		log("certain that their select inputs are mutually exclusive.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE

From 15535112b7b4caa1da75274397c5a3ba885a7349 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 11:52:51 -0700
Subject: [PATCH 29/32] Fix spacing

---
 passes/opt/muxpack.cc | 40 ++++++++++++++++++++--------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index c8b226c78..4468e8734 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -52,30 +52,30 @@ struct ExclusiveDatabase
 			}
 			else continue;
 
-                        log_assert(!nonconst_sig.empty());
-                        log_assert(!const_sig.empty());
-                        sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,const_sig.as_const());
-                }
-        }
+			log_assert(!nonconst_sig.empty());
+			log_assert(!const_sig.empty());
+			sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,const_sig.as_const());
+		}
+	}
 
-        bool query(const SigSpec &sig) const
-        {
-                SigSpec nonconst_sig;
-                pool<Const> const_values;
+	bool query(const SigSpec &sig) const
+	{
+		SigSpec nonconst_sig;
+		pool<Const> const_values;
 
-                for (auto bit : sig.bits()) {
-                        auto it = sig_cmp_prev.find(bit);
-                        if (it == sig_cmp_prev.end())
-                                return false;
+		for (auto bit : sig.bits()) {
+			auto it = sig_cmp_prev.find(bit);
+			if (it == sig_cmp_prev.end())
+				return false;
 
-                        if (nonconst_sig.empty())
-                                nonconst_sig = it->second.first;
-                        else if (nonconst_sig != it->second.first)
-                                return false;
+			if (nonconst_sig.empty())
+				nonconst_sig = it->second.first;
+			else if (nonconst_sig != it->second.first)
+				return false;
 
-                        if (!const_values.insert(it->second.second).second)
-                                return false;
-                }
+			if (!const_values.insert(it->second.second).second)
+				return false;
+		}
 
 		return true;
 	}

From ae8305ffcc0c812488163bcc35365d473ce1345d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 12:13:00 -0700
Subject: [PATCH 30/32] Fix testcase

---
 tests/various/muxpack.ys | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index ef8a6dab9..de5eec87f 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -230,13 +230,14 @@ sat -verify -prove-asserts -show-ports miter
 
 design -load read
 hierarchy -top case_overlap
-prep
+#prep # Do not prep otherwise $pmux's overlapping entry will get removed
+proc
 design -save gold
 muxpack
-#opt # Do not opt otherwise $pmux's overlapping entry will get removed
+opt
 stat
 select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 2 t:$pmux
 design -stash gate
 design -import gold -as gold
 design -import gate -as gate

From 32f637ffdb0c0641b51227fad92bc80e284740d2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 12:31:04 -0700
Subject: [PATCH 31/32] Add more tests

---
 tests/various/muxpack.v  | 47 +++++++++++++++++++++++-----------------
 tests/various/muxpack.ys | 25 ++++++++++++++++++++-
 2 files changed, 51 insertions(+), 21 deletions(-)

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 7a658d754..33ece1f16 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -187,7 +187,6 @@ module case_nonexclusive_select (
 );
         always @* begin
             case (x)
-                //0, 2: o = b;
                 0: o = b;
                 2: o = b;
                 1: o = c;
@@ -202,22 +201,16 @@ endmodule
 
 module case_nonoverlap (
         input wire [2:0] x,
-        input wire a, b, c, d, e, f, g,
+        input wire a, b, c, d, e,
         output reg o
 );
         always @* begin
             case (x)
-                //0, 2: o = b; // Creates $reduce_or
-                //0: o = b; 2: o = b; // Creates $reduce_or
-                0: o = b;
-                2: o = f;
+                0, 2: o = b; // Creates $reduce_or
                 1: o = c;
                 default:
                     case (x)
-                        //3, 4: o = d; // Creates $reduce_or
-                        //3: o = d; 4: o = d; // Creates $reduce_or
-                        3: o = d;
-                        4: o = g;
+                        3: o = d; 4: o = d; // Creates $reduce_or
                         5: o = e;
                         default: o = 1'b0;
                     endcase
@@ -227,23 +220,37 @@ endmodule
 
 module case_overlap (
         input wire [2:0] x,
-        input wire a, b, c, d, e, f, g,
+        input wire a, b, c, d, e,
         output reg o
 );
         always @* begin
             case (x)
-                //0, 2: o = b; // Creates $reduce_or
-                //0: o = b; 2: o = b; // Creates $reduce_or
-                0: o = b;
-                2: o = f;
+                0, 2: o = b; // Creates $reduce_or
                 1: o = c;
                 default:
                     case (x)
-                        //3, 4: o = d; // Creates $reduce_or
-                        //3: o = d; 4: o = d; // Creates $reduce_or
-                        2: o = 1'b1; // Overlaps with previous $pmux
-                        3: o = d;
-                        4: o = g;
+                        0: o = 1'b1; // OVERLAP!
+                        3, 4: o = d; // Creates $reduce_or
+                        5: o = e;
+                        default: o = 1'b0;
+                    endcase
+        endcase
+        end
+endmodule
+
+module case_overlap2 (
+        input wire [2:0] x,
+        input wire a, b, c, d, e,
+        output reg o
+);
+        always @* begin
+            case (x)
+                0: o = b; 2: o = b; // Creates $reduce_or
+                1: o = c;
+                default:
+                    case (x)
+                        0: o = d; 2: o = d; // Creates $reduce_or
+                        3: o = d; 4: o = d; // Creates $reduce_or
                         5: o = e;
                         default: o = 1'b0;
                     endcase
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index de5eec87f..af23fcec8 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -215,8 +215,11 @@ sat -verify -prove-asserts -show-ports miter
 
 design -load read
 hierarchy -top case_nonoverlap
-prep
+#prep # Do not prep otherwise $pmux's overlapping entry will get removed
+proc
 design -save gold
+opt -fast -mux_undef
+select -assert-count 2 t:$pmux
 muxpack
 opt
 stat
@@ -233,6 +236,26 @@ hierarchy -top case_overlap
 #prep # Do not prep otherwise $pmux's overlapping entry will get removed
 proc
 design -save gold
+opt -fast -mux_undef
+select -assert-count 2 t:$pmux
+muxpack
+opt
+stat
+select -assert-count 0 t:$mux
+select -assert-count 2 t:$pmux
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+design -load read
+hierarchy -top case_overlap2
+#prep # Do not prep otherwise $pmux's overlapping entry will get removed
+proc
+design -save gold
+opt -fast -mux_undef
+select -assert-count 2 t:$pmux
 muxpack
 opt
 stat

From 545cfbbe0dcc36f18dce6429498f4d87112879e2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 12:31:14 -0700
Subject: [PATCH 32/32] Cope with $reduce_or common in case

---
 passes/opt/muxpack.cc | 42 +++++++++++++++++++++++++++++++++++++-----
 1 file changed, 37 insertions(+), 5 deletions(-)

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 4468e8734..6697d6ca1 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -29,11 +29,13 @@ struct ExclusiveDatabase
 	Module *module;
 	const SigMap &sigmap;
 
-	dict<SigBit, std::pair<SigSpec,Const>> sig_cmp_prev;
+	dict<SigBit, std::pair<SigSpec,std::vector<Const>>> sig_cmp_prev;
 
 	ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
 	{
-		SigSpec const_sig, nonconst_sig, y_port;
+		SigSpec const_sig, nonconst_sig;
+		SigBit y_port;
+		pool<Cell*> reduce_or;
 		for (auto cell : module->cells()) {
 			if (cell->type == "$eq") {
 				nonconst_sig = sigmap(cell->getPort("\\A"));
@@ -50,11 +52,40 @@ struct ExclusiveDatabase
 				const_sig = Const(RTLIL::S0, GetSize(nonconst_sig));
 				y_port = sigmap(cell->getPort("\\Y"));
 			}
+			else if (cell->type == "$reduce_or") {
+				reduce_or.insert(cell);
+				continue;
+			}
 			else continue;
 
 			log_assert(!nonconst_sig.empty());
 			log_assert(!const_sig.empty());
-			sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,const_sig.as_const());
+			sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::vector<Const>{const_sig.as_const()});
+		}
+
+		for (auto cell : reduce_or) {
+			nonconst_sig = SigSpec();
+			std::vector<Const> values;
+			SigSpec a_port = sigmap(cell->getPort("\\A"));
+			for (auto bit : a_port) {
+				auto it = sig_cmp_prev.find(bit);
+				if (it == sig_cmp_prev.end()) {
+					nonconst_sig = SigSpec();
+					break;
+				}
+				if (nonconst_sig.empty())
+					nonconst_sig = it->second.first;
+				else if (nonconst_sig != it->second.first) {
+					nonconst_sig = SigSpec();
+					break;
+				}
+				for (auto value : it->second.second)
+					values.push_back(value);
+			}
+			if (nonconst_sig.empty())
+				continue;
+			y_port = sigmap(cell->getPort("\\Y"));
+			sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::move(values));
 		}
 	}
 
@@ -73,8 +104,9 @@ struct ExclusiveDatabase
 			else if (nonconst_sig != it->second.first)
 				return false;
 
-			if (!const_values.insert(it->second.second).second)
-				return false;
+			for (auto value : it->second.second)
+				if (!const_values.insert(value).second)
+					return false;
 		}
 
 		return true;