From e7156c644ded014febfa202593d718aa098b54dd Mon Sep 17 00:00:00 2001
From: CORRADI Quentin <12198691+dwRchyngqxs@users.noreply.github.com>
Date: Thu, 18 May 2023 14:46:25 +0100
Subject: [PATCH] Standard compliance for tests/verilog/block_labels.ys

genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration.
Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
---
 tests/verilog/block_labels.ys | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/verilog/block_labels.ys b/tests/verilog/block_labels.ys
index e76bcf771..76aad29ae 100644
--- a/tests/verilog/block_labels.ys
+++ b/tests/verilog/block_labels.ys
@@ -1,7 +1,7 @@
 read_verilog <<EOT
 module foo;
 
-	genvar a = 0;
+	genvar a;
 	for (a = 0; a < 10; a++) begin : a
 	end : a
 endmodule
@@ -9,7 +9,7 @@ EOT
 read_verilog <<EOT
 module foo2;
 
-	genvar a = 0;
+	genvar a;
 	for (a = 0; a < 10; a++) begin : a
 	end
 endmodule
@@ -19,7 +19,7 @@ logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
 read_verilog <<EOT
 module foo3;
 
-	genvar a = 0;
+	genvar a;
 	for (a = 0; a < 10; a++) begin : a
 	end : b
 endmodule