Added module->design and cell->module, wire->module pointers

frontends/ast/ast.cc

@@ -936,7 +936,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			(*it)->str = (*it)->str.substr(1);
 		if (defer)
 			(*it)->str = "$abstract" + (*it)->str;
-		if (design->modules_.count((*it)->str)) {
+		if (design->has((*it)->str)) {
 			if (!ignore_redef)
 				log_error("Re-definition of module `%s' at %s:%d!\n",
 						(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
@@ -944,7 +944,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 					(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
 			continue;
 		}
-		design->modules_[(*it)->str] =  process_module(*it, defer);
+		design->add(process_module(*it, defer));
 	}
 }
 
@@ -1041,10 +1041,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
 		modname = "$paramod" + stripped_name + para_info;
 	}
 
-	if (design->modules_.count(modname) == 0) {
+	if (!design->has(modname)) {
 		new_ast->str = modname;
-		design->modules_[modname] = process_module(new_ast, false);
+		design->add(process_module(new_ast, false));
-		design->modules_[modname]->check();
+		design->module(modname)->check();
 	} else {
 		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
 	}

frontends/ilang/parser.y

@@ -90,12 +90,12 @@ design:
 
 module:
 	TOK_MODULE TOK_ID EOL {
-		if (current_design->modules_.count($2) != 0)
+		if (current_design->has($2))
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
 		current_module = new RTLIL::Module;
 		current_module->name = $2;
 		current_module->attributes = attrbuf;
-		current_design->modules_[$2] = current_module;
+		current_design->add(current_module);
 		attrbuf.clear();
 		free($2);
 	} module_body TOK_END {

frontends/liberty/liberty.cc

@@ -477,7 +477,7 @@ struct LibertyFrontend : public Frontend {
 
 			std::string cell_name = RTLIL::escape_id(cell->args.at(0));
 
-			if (design->modules_.count(cell_name)) {
+			if (design->has(cell_name)) {
 				if (flag_ignore_redef)
 					continue;
 				log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
@@ -565,7 +565,7 @@ struct LibertyFrontend : public Frontend {
 			}
 
 			module->fixup_ports();
-			design->modules_[module->name] = module;
+			design->add(module);
 			cell_count++;
 skip_cell:;
 		}

frontends/verific/verific.cc

@@ -482,7 +482,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 {
 	std::string module_name = nl->IsOperator() ? std::string("$verific$") + nl->Owner()->Name() : RTLIL::escape_id(nl->Owner()->Name());
 
-	if (design->modules_.count(module_name)) {
+	if (design->has(module_name)) {
 		if (!nl->IsOperator())
 			log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
 		return;
@@ -490,7 +490,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 
 	RTLIL::Module *module = new RTLIL::Module;
 	module->name = module_name;
-	design->modules_[module->name] = module;
+	design->add(module);
 
 	log("Importing module %s.\n", RTLIL::id2cstr(module->name));
 

kernel/rtlil.cc

@@ -243,6 +243,7 @@ void RTLIL::Design::add(RTLIL::Module *module)
 	log_assert(modules_.count(module->name) == 0);
 	log_assert(refcount_modules_ == 0);
 	modules_[module->name] = module;
+	module->design = this;
 }
 
 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
@@ -250,6 +251,7 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
 	log_assert(modules_.count(name) == 0);
 	log_assert(refcount_modules_ == 0);
 	modules_[name] = new RTLIL::Module;
+	modules_[name]->design = this;
 	modules_[name]->name = name;
 	return modules_[name];
 }
@@ -265,6 +267,7 @@ void RTLIL::Design::check()
 {
 #ifndef NDEBUG
 	for (auto &it : modules_) {
+		log_assert(this == it.second->design);
 		log_assert(it.first == it.second->name);
 		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 		it.second->check();
@@ -319,6 +322,38 @@ bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
 	return selected_whole_module(mod->name);
 }
 
+std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
+{
+	std::vector<RTLIL::Module*> result;
+	result.reserve(modules_.size());
+	for (auto &it : modules_)
+		if (selected_module(it.first))
+			result.push_back(it.second);
+	return result;
+}
+
+std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
+{
+	std::vector<RTLIL::Module*> result;
+	result.reserve(modules_.size());
+	for (auto &it : modules_)
+		if (selected_whole_module(it.first))
+			result.push_back(it.second);
+	return result;
+}
+
+std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
+{
+	std::vector<RTLIL::Module*> result;
+	result.reserve(modules_.size());
+	for (auto &it : modules_)
+		if (selected_whole_module(it.first))
+			result.push_back(it.second);
+		else if (selected_module(it.first))
+			log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
+	return result;
+}
+
 RTLIL::Module::Module()
 {
 	refcount_wires_ = 0;
@@ -763,6 +798,7 @@ void RTLIL::Module::check()
 {
 #ifndef NDEBUG
 	for (auto &it : wires_) {
+		log_assert(this == it.second->module);
 		log_assert(it.first == it.second->name);
 		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 		log_assert(it.second->width >= 0);
@@ -783,6 +819,7 @@ void RTLIL::Module::check()
 	}
 
 	for (auto &it : cells_) {
+		log_assert(this == it.second->module);
 		log_assert(it.first == it.second->name);
 		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 		log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
@@ -868,12 +905,57 @@ RTLIL::Module *RTLIL::Module::clone() const
 	return new_mod;
 }
 
+bool RTLIL::Module::has_memories() const
+{
+	return !memories.empty();
+}
+
+bool RTLIL::Module::has_processes() const
+{
+	return !processes.empty();
+}
+
+bool RTLIL::Module::has_memories_warn() const
+{
+	if (!memories.empty())
+		log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
+	return !memories.empty();
+}
+
+bool RTLIL::Module::has_processes_warn() const
+{
+	if (!processes.empty())
+		log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
+	return !processes.empty();
+}
+
+std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
+{
+	std::vector<RTLIL::Wire*> result;
+	result.reserve(wires_.size());
+	for (auto &it : wires_)
+		if (design->selected(this, it.second))
+			result.push_back(it.second);
+	return result;
+}
+
+std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
+{
+	std::vector<RTLIL::Cell*> result;
+	result.reserve(wires_.size());
+	for (auto &it : cells_)
+		if (design->selected(this, it.second))
+			result.push_back(it.second);
+	return result;
+}
+
 void RTLIL::Module::add(RTLIL::Wire *wire)
 {
 	log_assert(!wire->name.empty());
 	log_assert(count_id(wire->name) == 0);
 	log_assert(refcount_wires_ == 0);
 	wires_[wire->name] = wire;
+	wire->module = this;
 }
 
 void RTLIL::Module::add(RTLIL::Cell *cell)
@@ -882,6 +964,7 @@ void RTLIL::Module::add(RTLIL::Cell *cell)
 	log_assert(count_id(cell->name) == 0);
 	log_assert(refcount_cells_ == 0);
 	cells_[cell->name] = cell;
+	cell->module = this;
 }
 
 namespace {

kernel/rtlil.h

@@ -252,6 +252,10 @@ namespace RTLIL
 		RTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }
 		RTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }
 
+		size_t size() const {
+			return list_p->size();
+		}
+
 		operator std::set<T>() const {
 			std::set<T> result;
 			for (auto &it : *list_p)
@@ -375,6 +379,10 @@ struct RTLIL::Design
 			sel.select(module, member);
 		}
 	}
+
+	std::vector<RTLIL::Module*> selected_modules() const;
+	std::vector<RTLIL::Module*> selected_whole_modules() const;
+	std::vector<RTLIL::Module*> selected_whole_modules_warn() const;
 };
 
 #define RTLIL_ATTRIBUTE_MEMBERS                                \
@@ -395,6 +403,7 @@ protected:
 	void add(RTLIL::Cell *cell);
 
 public:
+	RTLIL::Design *design;
 	int refcount_wires_;
 	int refcount_cells_;
 
@@ -424,6 +433,15 @@ public:
 	void cloneInto(RTLIL::Module *new_mod) const;
 	virtual RTLIL::Module *clone() const;
 
+	bool has_memories() const;
+	bool has_processes() const;
+
+	bool has_memories_warn() const;
+	bool has_processes_warn() const;
+
+	std::vector<RTLIL::Wire*> selected_wires() const;
+	std::vector<RTLIL::Cell*> selected_cells() const;
+
 	RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; }
 	RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; }
 
@@ -592,6 +610,7 @@ public:
 	Wire(RTLIL::Wire &other) = delete;
 	void operator=(RTLIL::Wire &other) = delete;
 
+	RTLIL::Module *module;
 	RTLIL::IdString name;
 	int width, start_offset, port_id;
 	bool port_input, port_output, upto;
@@ -620,6 +639,7 @@ public:
 	Cell(RTLIL::Cell &other) = delete;
 	void operator=(RTLIL::Cell &other) = delete;
 
+	RTLIL::Module *module;
 	RTLIL::IdString name;
 	RTLIL::IdString type;
 	std::map<RTLIL::IdString, RTLIL::SigSpec> connections_;

manual/PRESENTATION_Prog/Makefile

@@ -5,14 +5,14 @@ my_cmd.so: my_cmd.cc
 	../../yosys-config --exec --cxx --cxxflags --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
 
 test0.log: my_cmd.so
-	../../yosys -l test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
+	../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
 	mv test0.log_new test0.log
 
 test1.log: my_cmd.so
-	../../yosys -l test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
+	../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
 	mv test1.log_new test1.log
 
 test2.log: my_cmd.so
-	../../yosys -l test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
+	../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
 	mv test2.log_new test2.log
 

manual/PRESENTATION_Prog/my_cmd.cc

@@ -1,6 +1,4 @@
-#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
-#include "kernel/register.h"
-#include "kernel/log.h"
 #include "kernel/sigtools.h"
 
 struct MyPass : public Pass {
@@ -12,9 +10,9 @@ struct MyPass : public Pass {
             log("  %s\n", arg.c_str());
 
         log("Modules in current design:\n");
-        for (auto &mod : design->modules_)
+        for (auto mod : design->modules())
-            log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
+            log("  %s (%zd wires, %zd cells)\n", log_id(mod),
-                    mod.second->wires_.size(), mod.second->cells_.size());
+                    SIZE(mod->wires()), SIZE(mod->cells()));
     }
 } MyPass;
 
@@ -23,28 +21,24 @@ struct Test1Pass : public Pass {
     Test1Pass() : Pass("test1", "creating the absval module") { }
     virtual void execute(std::vector<std::string>, RTLIL::Design *design)
     {
-        RTLIL::Module *module = new RTLIL::Module;
+        if (design->has("\\absval") != 0)
-        module->name = "\\absval";
+            log_error("A module with the name absval already exists!\n");
 
-        RTLIL::Wire *a = module->new_wire(4, "\\a");
+        RTLIL::Module *module = design->addModule("\\absval");
+
+        RTLIL::Wire *a = module->addWire("\\a", 4);
         a->port_input = true;
         a->port_id = 1;
 
-        RTLIL::Wire *y = module->new_wire(4, "\\y");
+        RTLIL::Wire *y = module->addWire("\\y", 4);
         y->port_output = true;
         y->port_id = 2;
 
-        RTLIL::Wire *a_inv = module->new_wire(4, NEW_ID);
+        RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
         module->addNeg(NEW_ID, a, a_inv, true);
-        module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y);
+        module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
 
-        log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
+        log("Name of this module: %s\n", log_id(module));
-
-        if (design->modules_.count(module->name) != 0)
-            log_error("A module with the name %s already exists!\n",
-                    RTLIL::id2cstr(module->name));
-
-        design->modules_[module->name] = module;
     }
 } Test1Pass;
 
@@ -58,8 +52,7 @@ struct Test2Pass : public Pass {
 
         RTLIL::Module *module = design->modules_.at("\\test");
 
-        RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
+        RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")), y(module->wire("\\y"));
-                                                   y(module->wires_.at("\\y"));
         log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
 
         SigMap sigmap(module);

passes/abc/blifparse.cc

@@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 
 	int port_count = 0;
 	module->name = "\\netlist";
-	design->modules_[module->name] = module;
+	design->add(module);
 
 	size_t buffer_size = 4096;
 	char *buffer = (char*)malloc(buffer_size);

passes/cmds/copy.cc

@@ -47,8 +47,9 @@ struct CopyPass : public Pass {
 		if (design->modules_.count(trg_name) != 0)
 			log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
 
-		design->modules_[trg_name] = design->modules_.at(src_name)->clone();
+		RTLIL::Module *new_mod = design->module(src_name)->clone();
-		design->modules_[trg_name]->name = trg_name;
+		new_mod->name = trg_name;
+		design->add(new_mod);
 	}
 } CopyPass;
  

passes/cmds/design.cc

@@ -198,6 +198,7 @@ struct DesignPass : public Pass {
 					delete copy_to_design->modules_.at(trg_name);
 				copy_to_design->modules_[trg_name] = mod->clone();
 				copy_to_design->modules_[trg_name]->name = trg_name;
+				copy_to_design->modules_[trg_name]->design = copy_to_design;
 			}
 		}
 
@@ -206,7 +207,7 @@ struct DesignPass : public Pass {
 			RTLIL::Design *design_copy = new RTLIL::Design;
 
 			for (auto &it : design->modules_)
-				design_copy->modules_[it.first] = it.second->clone();
+				design_copy->add(it.second->clone());
 
 			design_copy->selection_stack = design->selection_stack;
 			design_copy->selection_vars = design->selection_vars;
@@ -242,7 +243,7 @@ struct DesignPass : public Pass {
 				pushed_designs.pop_back();
 
 			for (auto &it : saved_design->modules_)
-				design->modules_[it.first] = it.second->clone();
+				design->add(it.second->clone());
 
 			design->selection_stack = saved_design->selection_stack;
 			design->selection_vars = saved_design->selection_vars;

passes/hierarchy/hierarchy.cc

@@ -117,7 +117,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
 		mod->attributes["\\blackbox"] = RTLIL::Const(1);
-		design->modules_[mod->name] = mod;
+		design->add(mod);
 
 		for (auto &decl : ports) {
 			RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));

passes/hierarchy/submod.cc

@@ -105,7 +105,7 @@ struct SubmodWorker
 
 		RTLIL::Module *new_mod = new RTLIL::Module;
 		new_mod->name = submod.full_name;
-		design->modules_[new_mod->name] = new_mod;
+		design->add(new_mod);
 		int port_counter = 1, auto_name_counter = 1;
 
 		std::set<std::string> all_wire_names;

passes/sat/miter.cc

@@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 
 	RTLIL::Module *miter_module = new RTLIL::Module;
 	miter_module->name = miter_name;
-	design->modules_[miter_name] = miter_module;
+	design->add(miter_module);
 
 	RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
 	RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);

passes/techmap/extract.cc

@@ -724,7 +724,7 @@ struct ExtractPass : public Pass {
 
 				RTLIL::Module *newMod = new RTLIL::Module;
 				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
-				map->modules_[newMod->name] = newMod;
+				map->add(newMod);
 
 				int portCounter = 1;
 				for (auto wire : wires) {