mirror of https://github.com/YosysHQ/yosys.git
opt_mem: Add reset/init value support.
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24b880b2de
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@ -51,6 +51,8 @@ struct OptMemPass : public Pass {
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int total_count = 0;
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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FfInitVals initvals(&sigmap, module);
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for (auto &mem : Mem::get_selected_memories(module)) {
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for (auto &mem : Mem::get_selected_memories(module)) {
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bool changed = false;
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bool changed = false;
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for (auto &port : mem.wr_ports) {
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for (auto &port : mem.wr_ports) {
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@ -65,6 +67,16 @@ struct OptMemPass : public Pass {
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}
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}
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if (mem.wr_ports.empty() && mem.inits.empty()) {
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if (mem.wr_ports.empty() && mem.inits.empty()) {
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// The whole memory array will contain
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// only State::Sx, but the embedded read
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// registers could have reset or init values.
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// They will probably be optimized away by
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// opt_dff later.
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for (int i = 0; i < GetSize(mem.rd_ports); i++) {
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mem.extract_rdff(i, &initvals);
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auto &port = mem.rd_ports[i];
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module->connect(port.data, Const(State::Sx, GetSize(port.data)));
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}
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mem.remove();
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mem.remove();
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total_count++;
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total_count++;
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}
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}
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