riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Improvements in new SigMap

This commit is contained in:
Clifford Wolf 2015-10-28 00:39:53 +01:00
parent 0c202a2549
commit e69efec588
1 changed files with 16 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
kernel/sigtools.h
View File

@ -253,18 +253,29 @@ struct SigMap
for (int i = 0; i < GetSize(from); i++)
{
RTLIL::SigBit &bf = from[i];
RTLIL::SigBit &bt = to[i];
RTLIL::SigBit bf = database.find(from[i]);
RTLIL::SigBit bt = database.find(to[i]);
if (bf.wire != nullptr)
if (bf.wire || bt.wire)
{
database.merge(bf, bt);
if (bf.wire == nullptr)
database.promote(bf);
if (bt.wire == nullptr)
database.promote(bt);
}
}
}
void add(RTLIL::SigSpec sig)
{
for (auto &bit : sig)
database.promote(bit);
for (auto &bit : sig) {
RTLIL::SigBit b = database.find(bit);
if (b.wire != nullptr)
database.promote(bit);
}
}
void apply(RTLIL::SigBit &bit) const