mirror of https://github.com/YosysHQ/yosys.git
Improvements in new SigMap
This commit is contained in:
parent
0c202a2549
commit
e69efec588
|
@ -253,18 +253,29 @@ struct SigMap
|
||||||
|
|
||||||
for (int i = 0; i < GetSize(from); i++)
|
for (int i = 0; i < GetSize(from); i++)
|
||||||
{
|
{
|
||||||
RTLIL::SigBit &bf = from[i];
|
RTLIL::SigBit bf = database.find(from[i]);
|
||||||
RTLIL::SigBit &bt = to[i];
|
RTLIL::SigBit bt = database.find(to[i]);
|
||||||
|
|
||||||
if (bf.wire != nullptr)
|
if (bf.wire || bt.wire)
|
||||||
|
{
|
||||||
database.merge(bf, bt);
|
database.merge(bf, bt);
|
||||||
|
|
||||||
|
if (bf.wire == nullptr)
|
||||||
|
database.promote(bf);
|
||||||
|
|
||||||
|
if (bt.wire == nullptr)
|
||||||
|
database.promote(bt);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void add(RTLIL::SigSpec sig)
|
void add(RTLIL::SigSpec sig)
|
||||||
{
|
{
|
||||||
for (auto &bit : sig)
|
for (auto &bit : sig) {
|
||||||
database.promote(bit);
|
RTLIL::SigBit b = database.find(bit);
|
||||||
|
if (b.wire != nullptr)
|
||||||
|
database.promote(bit);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void apply(RTLIL::SigBit &bit) const
|
void apply(RTLIL::SigBit &bit) const
|
||||||
|
|
Loading…
Reference in New Issue