diff --git a/CHANGELOG b/CHANGELOG
index 24c81be6e..51ff4e1a4 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -22,9 +22,9 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
+    - Added "synth -abc9" (experimental)
     - Extended "muxcover -mux{4,8,16}=<cost>"
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
-    - Added "synth -abc9" (experimental)
     - Added "muxpack" pass
     - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)